module ysyx_22051110_RegFileV(
   input          clock,
   input          reset,
   input  [4:0]  waddr,
   input  [4:0]  raddr1,
   input  [4:0]  raddr2,
   input          wen,
   input  [63:0]  wdata,
   output [63:0]  rdata1,
   output [63:0]  rdata2
);
    reg[63:0] reg_file[31:0];
    always@(posedge clock) begin
        if (reset) begin
            reg_file[0] <= 64'b0;
            reg_file[1] <= 64'b0;
            reg_file[2] <= 64'b0;
            reg_file[3] <= 64'b0;
            reg_file[4] <= 64'b0;
            reg_file[5] <= 64'b0;
            reg_file[6] <= 64'b0;
            reg_file[7] <= 64'b0;
            reg_file[8] <= 64'b0;
            reg_file[9] <= 64'b0;
            reg_file[10] <= 64'b0;
            reg_file[11] <= 64'b0;
            reg_file[12] <= 64'b0;
            reg_file[13] <= 64'b0;
            reg_file[14] <= 64'b0;
            reg_file[15] <= 64'b0;
            reg_file[16] <= 64'b0;
            reg_file[17] <= 64'b0;
            reg_file[18] <= 64'b0;
            reg_file[19] <= 64'b0;
            reg_file[20] <= 64'b0;
            reg_file[21] <= 64'b0;
            reg_file[22] <= 64'b0;
            reg_file[23] <= 64'b0;
            reg_file[24] <= 64'b0;
            reg_file[25] <= 64'b0;
            reg_file[26] <= 64'b0;
            reg_file[27] <= 64'b0;
            reg_file[28] <= 64'b0;
            reg_file[29] <= 64'b0;
            reg_file[30] <= 64'b0;
            reg_file[31] <= 64'b0;
        end
        else if(wen && (waddr != 5'b0)) begin
            reg_file[waddr] <= wdata[63:0];
        end
    end
    assign rdata1[63:0] = raddr1==0? 0: reg_file[raddr1];
    assign rdata2[63:0] = raddr2==0? 0: reg_file[raddr2];
endmodule
module ysyx_22051110_CacheMetaRamV(
    input clock        , input reset , input flush        , input en, input wr,
    output valid       , output dirty, output [22 : 0] tag,
    input [5 : 0] addr , input wvalid, input wdirty      ,
    input [22 : 0] wtag
);
    reg [22 : 0] ram_tag[63 : 0];
    reg [63 : 0] ram_valid;
    reg [63 : 0] ram_dirty;
    reg [22 : 0] rtag;
    reg rvalid, rdirty;
    always @(posedge clock) begin
        if(reset | flush) begin
            rtag   <= 23'b0;
            rvalid <= 1'b0;
            rdirty <= 1'b0;
            ram_valid[63 : 0] <= 64'b0;
            ram_dirty[63 : 0] <= 64'b0;
            ram_tag[0] <= 23'b0;
            ram_tag[1] <= 23'b0;
            ram_tag[2] <= 23'b0;
            ram_tag[3] <= 23'b0;
            ram_tag[4] <= 23'b0;
            ram_tag[5] <= 23'b0;
            ram_tag[6] <= 23'b0;
            ram_tag[7] <= 23'b0;
            ram_tag[8] <= 23'b0;
            ram_tag[9] <= 23'b0;
            ram_tag[10] <= 23'b0;
            ram_tag[11] <= 23'b0;
            ram_tag[12] <= 23'b0;
            ram_tag[13] <= 23'b0;
            ram_tag[14] <= 23'b0;
            ram_tag[15] <= 23'b0;
            ram_tag[16] <= 23'b0;
            ram_tag[17] <= 23'b0;
            ram_tag[18] <= 23'b0;
            ram_tag[19] <= 23'b0;
            ram_tag[20] <= 23'b0;
            ram_tag[21] <= 23'b0;
            ram_tag[22] <= 23'b0;
            ram_tag[23] <= 23'b0;
            ram_tag[24] <= 23'b0;
            ram_tag[25] <= 23'b0;
            ram_tag[26] <= 23'b0;
            ram_tag[27] <= 23'b0;
            ram_tag[28] <= 23'b0;
            ram_tag[29] <= 23'b0;
            ram_tag[30] <= 23'b0;
            ram_tag[31] <= 23'b0;
            ram_tag[32] <= 23'b0;
            ram_tag[33] <= 23'b0;
            ram_tag[34] <= 23'b0;
            ram_tag[35] <= 23'b0;
            ram_tag[36] <= 23'b0;
            ram_tag[37] <= 23'b0;
            ram_tag[38] <= 23'b0;
            ram_tag[39] <= 23'b0;
            ram_tag[40] <= 23'b0;
            ram_tag[41] <= 23'b0;
            ram_tag[42] <= 23'b0;
            ram_tag[43] <= 23'b0;
            ram_tag[44] <= 23'b0;
            ram_tag[45] <= 23'b0;
            ram_tag[46] <= 23'b0;
            ram_tag[47] <= 23'b0;
            ram_tag[48] <= 23'b0;
            ram_tag[49] <= 23'b0;
            ram_tag[50] <= 23'b0;
            ram_tag[51] <= 23'b0;
            ram_tag[52] <= 23'b0;
            ram_tag[53] <= 23'b0;
            ram_tag[54] <= 23'b0;
            ram_tag[55] <= 23'b0;
            ram_tag[56] <= 23'b0;
            ram_tag[57] <= 23'b0;
            ram_tag[58] <= 23'b0;
            ram_tag[59] <= 23'b0;
            ram_tag[60] <= 23'b0;
            ram_tag[61] <= 23'b0;
            ram_tag[62] <= 23'b0;
            ram_tag[63] <= 23'b0;
        end
        else if(en && wr) begin
            ram_tag[addr]   <= wtag;
            ram_valid[addr] <= wvalid;
            ram_dirty[addr] <= wdirty;
        end
        if(en && !wr) begin
            rtag   <= ram_tag[addr];
            rvalid <= ram_valid[addr];
            rdirty <= ram_dirty[addr];
        end
    end
    assign valid = rvalid;
    assign dirty = rdirty;
    assign tag   = rtag;
endmodule
module ysyx_22051110_MemoryMappingUnit(
  input  [31:0] io_addr_in,
  output        io_mthrough
);
  wire [2:0] hi = io_addr_in[31:29]; // @[MM.scala 47:24]
  wire  _no_mem_T_3 = hi[1:0] != 2'h0; // @[MM.scala 49:28]
  assign io_mthrough = ~hi[2] | _no_mem_T_3; // @[MM.scala 48:27]
endmodule
module ysyx_22051110_If_stage(
  input         clock,
  input         reset,
  input  [31:0] io_branch_br_target,
  input         io_branch_br_en,
  input         io_inst_mem_req_ready,
  output        io_inst_mem_req_valid,
  output [31:0] io_inst_mem_req_bits_addr,
  output        io_inst_mem_req_bits_mthrough,
  input  [63:0] io_inst_mem_ret_rdata,
  input         io_inst_mem_ret_valid,
  input         io_if2id_ready,
  output        io_if2id_valid,
  output [31:0] io_if2id_bits_inst,
  output [31:0] io_if2id_bits_pc,
  input         io_exc_br_exc_br,
  input  [31:0] io_exc_br_exc_target
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [63:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] mm_io_addr_in; // @[If_stage.scala 33:27]
  wire  mm_io_mthrough; // @[If_stage.scala 33:27]
  reg [31:0] pc; // @[If_stage.scala 27:28]
  wire [31:0] _nextpc_T_1 = pc + 32'h4; // @[If_stage.scala 29:74]
  wire [31:0] _nextpc_T_2 = io_branch_br_en ? io_branch_br_target : _nextpc_T_1; // @[If_stage.scala 29:32]
  wire [31:0] nextpc = io_exc_br_exc_br ? io_exc_br_exc_target : _nextpc_T_2; // @[If_stage.scala 28:24]
  reg  fs_wait_r; // @[If_stage.scala 30:29]
  reg [5:0] fs_state; // @[If_stage.scala 31:28]
  reg [31:0] nextpc_r; // @[If_stage.scala 32:28]
  wire  _fs_state_T_2 = io_exc_br_exc_br | io_branch_br_en; // @[If_stage.scala 36:61]
  wire  _fs_state_T_3 = io_inst_mem_req_ready & io_inst_mem_req_valid; // @[Decoupled.scala 52:35]
  wire [5:0] _fs_state_T_4 = _fs_state_T_3 ? 6'h20 : 6'h10; // @[If_stage.scala 37:65]
  wire [2:0] _fs_state_T_6 = _fs_state_T_3 ? 3'h4 : 3'h2; // @[If_stage.scala 38:65]
  wire [5:0] _fs_state_T_7 = io_exc_br_exc_br | io_branch_br_en ? _fs_state_T_4 : {{3'd0}, _fs_state_T_6}; // @[If_stage.scala 36:43]
  wire [4:0] _fs_state_T_10 = io_inst_mem_ret_valid ? 5'h10 : 5'h8; // @[If_stage.scala 40:65]
  wire [2:0] _fs_state_T_11 = io_inst_mem_ret_valid ? 3'h2 : 3'h4; // @[If_stage.scala 41:65]
  wire [4:0] _fs_state_T_12 = _fs_state_T_2 ? _fs_state_T_10 : {{2'd0}, _fs_state_T_11}; // @[If_stage.scala 39:43]
  wire [4:0] _fs_state_T_16 = io_exc_br_exc_br ? _fs_state_T_10 : _fs_state_T_10; // @[If_stage.scala 42:43]
  wire [4:0] _fs_state_T_19 = _fs_state_T_3 ? 5'h8 : 5'h10; // @[If_stage.scala 44:65]
  wire [5:0] _fs_state_T_22 = io_exc_br_exc_br ? {{1'd0}, _fs_state_T_19} : _fs_state_T_4; // @[If_stage.scala 44:43]
  wire [5:0] _fs_state_T_25 = io_inst_mem_ret_valid ? 6'h2 : 6'h20; // @[If_stage.scala 47:65]
  wire [5:0] _fs_state_T_26 = io_exc_br_exc_br ? {{1'd0}, _fs_state_T_10} : _fs_state_T_25; // @[If_stage.scala 46:43]
  wire [1:0] _fs_state_T_27 = fs_state[0] ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [5:0] _fs_state_T_28 = fs_state[1] ? _fs_state_T_7 : 6'h0; // @[Mux.scala 27:73]
  wire [4:0] _fs_state_T_29 = fs_state[2] ? _fs_state_T_12 : 5'h0; // @[Mux.scala 27:73]
  wire [4:0] _fs_state_T_30 = fs_state[3] ? _fs_state_T_16 : 5'h0; // @[Mux.scala 27:73]
  wire [5:0] _fs_state_T_31 = fs_state[4] ? _fs_state_T_22 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _fs_state_T_32 = fs_state[5] ? _fs_state_T_26 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _GEN_6 = {{4'd0}, _fs_state_T_27}; // @[Mux.scala 27:73]
  wire [5:0] _fs_state_T_33 = _GEN_6 | _fs_state_T_28; // @[Mux.scala 27:73]
  wire [5:0] _GEN_7 = {{1'd0}, _fs_state_T_29}; // @[Mux.scala 27:73]
  wire [5:0] _fs_state_T_34 = _fs_state_T_33 | _GEN_7; // @[Mux.scala 27:73]
  wire [5:0] _GEN_8 = {{1'd0}, _fs_state_T_30}; // @[Mux.scala 27:73]
  wire [5:0] _fs_state_T_35 = _fs_state_T_34 | _GEN_8; // @[Mux.scala 27:73]
  wire [5:0] _fs_state_T_36 = _fs_state_T_35 | _fs_state_T_31; // @[Mux.scala 27:73]
  wire [5:0] _fs_state_T_37 = _fs_state_T_36 | _fs_state_T_32; // @[Mux.scala 27:73]
  wire  _io_inst_mem_req_valid_T_3 = ~io_exc_br_exc_br; // @[If_stage.scala 50:68]
  reg [63:0] rdata_buf; // @[If_stage.scala 61:36]
  wire  _fs_mem_ok_T_1 = ~io_branch_br_en; // @[If_stage.scala 64:57]
  wire  _fs_mem_ok_T_2 = _io_inst_mem_req_valid_T_3 & ~io_branch_br_en; // @[If_stage.scala 64:54]
  wire  _fs_mem_ok_T_9 = _fs_mem_ok_T_2 & fs_state[2]; // @[If_stage.scala 65:74]
  wire  _fs_mem_ok_T_10 = _io_inst_mem_req_valid_T_3 & ~io_branch_br_en & fs_state[5] | _fs_mem_ok_T_9; // @[If_stage.scala 64:90]
  wire  fs_mem_ok = io_inst_mem_ret_valid & _fs_mem_ok_T_10; // @[If_stage.scala 63:51]
  wire [63:0] fs_inst_data = fs_wait_r ? rdata_buf : io_inst_mem_ret_rdata; // @[If_stage.scala 67:32]
  wire  _T_3 = io_if2id_ready & io_if2id_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_2 = fs_mem_ok & ~io_if2id_ready | fs_wait_r; // @[If_stage.scala 77:45 78:19 30:29]
  ysyx_22051110_MemoryMappingUnit mm ( // @[If_stage.scala 33:27]
    .io_addr_in(mm_io_addr_in),
    .io_mthrough(mm_io_mthrough)
  );
  assign io_inst_mem_req_valid = fs_state[1] & ~fs_wait_r & ~io_exc_br_exc_br | fs_state[4]; // @[If_stage.scala 50:87]
  assign io_inst_mem_req_bits_addr = fs_state[4] ? nextpc_r : nextpc; // @[If_stage.scala 52:41]
  assign io_inst_mem_req_bits_mthrough = mm_io_mthrough; // @[If_stage.scala 59:35]
  assign io_if2id_valid = (fs_mem_ok | fs_wait_r) & _io_inst_mem_req_valid_T_3 & _fs_mem_ok_T_1; // @[If_stage.scala 82:73]
  assign io_if2id_bits_inst = pc[2] ? fs_inst_data[63:32] : fs_inst_data[31:0]; // @[If_stage.scala 83:30]
  assign io_if2id_bits_pc = pc; // @[If_stage.scala 84:24]
  assign mm_io_addr_in = io_inst_mem_req_bits_addr; // @[If_stage.scala 58:35]
  always @(posedge clock) begin
    if (reset) begin // @[If_stage.scala 27:28]
      pc <= 32'h2ffffffc; // @[If_stage.scala 27:28]
    end else if (_fs_state_T_3) begin // @[If_stage.scala 69:32]
      if (fs_state[4]) begin // @[If_stage.scala 52:41]
        pc <= nextpc_r;
      end else if (io_exc_br_exc_br) begin // @[If_stage.scala 28:24]
        pc <= io_exc_br_exc_target;
      end else begin
        pc <= _nextpc_T_2;
      end
    end
    if (reset) begin // @[If_stage.scala 30:29]
      fs_wait_r <= 1'h0; // @[If_stage.scala 30:29]
    end else if (_fs_state_T_2 | fs_wait_r & _T_3) begin // @[If_stage.scala 75:78]
      fs_wait_r <= 1'h0; // @[If_stage.scala 76:19]
    end else begin
      fs_wait_r <= _GEN_2;
    end
    if (reset) begin // @[If_stage.scala 31:28]
      fs_state <= 6'h1; // @[If_stage.scala 31:28]
    end else begin
      fs_state <= _fs_state_T_37; // @[If_stage.scala 34:18]
    end
    if (reset) begin // @[If_stage.scala 32:28]
      nextpc_r <= 32'h0; // @[If_stage.scala 32:28]
    end else if (io_branch_br_en | io_exc_br_exc_br) begin // @[If_stage.scala 73:46]
      if (io_exc_br_exc_br) begin // @[If_stage.scala 28:24]
        nextpc_r <= io_exc_br_exc_target;
      end else if (io_branch_br_en) begin // @[If_stage.scala 29:32]
        nextpc_r <= io_branch_br_target;
      end else begin
        nextpc_r <= _nextpc_T_1;
      end
    end
    if (reset) begin // @[If_stage.scala 61:36]
      rdata_buf <= 64'h0; // @[If_stage.scala 61:36]
    end else if (!(_fs_state_T_2 | fs_wait_r & _T_3)) begin // @[If_stage.scala 75:78]
      if (fs_mem_ok & ~io_if2id_ready) begin // @[If_stage.scala 77:45]
        rdata_buf <= io_inst_mem_ret_rdata; // @[If_stage.scala 79:20]
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  pc = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  fs_wait_r = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  fs_state = _RAND_2[5:0];
  _RAND_3 = {1{`RANDOM}};
  nextpc_r = _RAND_3[31:0];
  _RAND_4 = {2{`RANDOM}};
  rdata_buf = _RAND_4[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_MyDecoder(
  input  [31:0] io_inst,
  output [5:0]  io_inst_type,
  output [22:0] io_alu_op,
  output        io_src1_sel,
  output        io_src2_sel,
  output        io_rf_we,
  output        io_wb_sel,
  output [8:0]  io_br_type,
  output        io_mem_en,
  output        io_mem_wr,
  output [6:0]  io_mem_type,
  output        io_rv64w,
  output [2:0]  io_ex_sel,
  output [2:0]  io_csr_op,
  output [2:0]  io_exc_type,
  output        io_op_muldiv
);
  wire [31:0] _csignals_T = io_inst & 32'h7f; // @[Lookup.scala 31:38]
  wire  _csignals_T_1 = 32'h37 == _csignals_T; // @[Lookup.scala 31:38]
  wire  _csignals_T_3 = 32'h17 == _csignals_T; // @[Lookup.scala 31:38]
  wire  _csignals_T_5 = 32'h6f == _csignals_T; // @[Lookup.scala 31:38]
  wire  _csignals_T_7 = 32'h67 == _csignals_T; // @[Lookup.scala 31:38]
  wire [31:0] _csignals_T_8 = io_inst & 32'h707f; // @[Lookup.scala 31:38]
  wire  _csignals_T_9 = 32'h63 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_11 = 32'h1063 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_13 = 32'h4063 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_15 = 32'h5063 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_17 = 32'h6063 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_19 = 32'h7063 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_21 = 32'h3 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_23 = 32'h1003 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_25 = 32'h2003 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_27 = 32'h4003 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_29 = 32'h5003 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_31 = 32'h6003 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_33 = 32'h3003 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_35 = 32'h23 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_37 = 32'h1023 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_39 = 32'h2023 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_41 = 32'h3023 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_43 = 32'h13 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_45 = 32'h2013 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_47 = 32'h3013 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_49 = 32'h4013 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_51 = 32'h6013 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_53 = 32'h7013 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire [31:0] _csignals_T_54 = io_inst & 32'hfc00707f; // @[Lookup.scala 31:38]
  wire  _csignals_T_55 = 32'h1013 == _csignals_T_54; // @[Lookup.scala 31:38]
  wire  _csignals_T_57 = 32'h5013 == _csignals_T_54; // @[Lookup.scala 31:38]
  wire  _csignals_T_59 = 32'h40005013 == _csignals_T_54; // @[Lookup.scala 31:38]
  wire  _csignals_T_61 = 32'h1b == _csignals_T_8; // @[Lookup.scala 31:38]
  wire [31:0] _csignals_T_62 = io_inst & 32'hfe00707f; // @[Lookup.scala 31:38]
  wire  _csignals_T_63 = 32'h101b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_65 = 32'h501b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_67 = 32'h4000501b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_69 = 32'h33 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_71 = 32'h40000033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_73 = 32'h1033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_75 = 32'h2033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_77 = 32'h3033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_79 = 32'h4033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_81 = 32'h5033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_83 = 32'h40005033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_85 = 32'h6033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_87 = 32'h7033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_89 = 32'h3b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_91 = 32'h4000003b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_93 = 32'h103b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_95 = 32'h503b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_97 = 32'h4000503b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_99 = 32'h2000033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_101 = 32'h2001033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_103 = 32'h2003033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_105 = 32'h2002033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_107 = 32'h200003b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_109 = 32'h2004033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_111 = 32'h2005033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_113 = 32'h200403b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_115 = 32'h200503b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_117 = 32'h2006033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_119 = 32'h2007033 == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_121 = 32'h200603b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_123 = 32'h200703b == _csignals_T_62; // @[Lookup.scala 31:38]
  wire  _csignals_T_125 = 32'h100f == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_127 = 32'h1073 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_129 = 32'h2073 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_131 = 32'h3073 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_133 = 32'h5073 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_135 = 32'h6073 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_137 = 32'h7073 == _csignals_T_8; // @[Lookup.scala 31:38]
  wire  _csignals_T_139 = 32'h73 == io_inst; // @[Lookup.scala 31:38]
  wire  _csignals_T_141 = 32'h30200073 == io_inst; // @[Lookup.scala 31:38]
  wire  _csignals_T_178 = _csignals_T_69 | (_csignals_T_71 | (_csignals_T_73 | (_csignals_T_75 | (_csignals_T_77 | (
    _csignals_T_79 | (_csignals_T_81 | (_csignals_T_83 | (_csignals_T_85 | (_csignals_T_87 | (_csignals_T_89 | (
    _csignals_T_91 | (_csignals_T_93 | (_csignals_T_95 | (_csignals_T_97 | (_csignals_T_99 | (_csignals_T_101 | (
    _csignals_T_103 | (_csignals_T_105 | (_csignals_T_107 | (_csignals_T_109 | (_csignals_T_111 | (_csignals_T_113 | (
    _csignals_T_115 | (_csignals_T_117 | (_csignals_T_119 | (_csignals_T_121 | _csignals_T_123))))))))))))))))))))))))))
    ; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_179 = _csignals_T_67 ? 2'h2 : {{1'd0}, _csignals_T_178}; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_180 = _csignals_T_65 ? 2'h2 : _csignals_T_179; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_181 = _csignals_T_63 ? 2'h2 : _csignals_T_180; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_182 = _csignals_T_61 ? 2'h2 : _csignals_T_181; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_183 = _csignals_T_59 ? 2'h2 : _csignals_T_182; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_184 = _csignals_T_57 ? 2'h2 : _csignals_T_183; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_185 = _csignals_T_55 ? 2'h2 : _csignals_T_184; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_186 = _csignals_T_53 ? 2'h2 : _csignals_T_185; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_187 = _csignals_T_51 ? 2'h2 : _csignals_T_186; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_188 = _csignals_T_49 ? 2'h2 : _csignals_T_187; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_189 = _csignals_T_47 ? 2'h2 : _csignals_T_188; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_190 = _csignals_T_45 ? 2'h2 : _csignals_T_189; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_191 = _csignals_T_43 ? 2'h2 : _csignals_T_190; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_192 = _csignals_T_41 ? 3'h4 : {{1'd0}, _csignals_T_191}; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_193 = _csignals_T_39 ? 3'h4 : _csignals_T_192; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_194 = _csignals_T_37 ? 3'h4 : _csignals_T_193; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_195 = _csignals_T_35 ? 3'h4 : _csignals_T_194; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_196 = _csignals_T_33 ? 3'h2 : _csignals_T_195; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_197 = _csignals_T_31 ? 3'h2 : _csignals_T_196; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_198 = _csignals_T_29 ? 3'h2 : _csignals_T_197; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_199 = _csignals_T_27 ? 3'h2 : _csignals_T_198; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_200 = _csignals_T_25 ? 3'h2 : _csignals_T_199; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_201 = _csignals_T_23 ? 3'h2 : _csignals_T_200; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_202 = _csignals_T_21 ? 3'h2 : _csignals_T_201; // @[Lookup.scala 34:39]
  wire [3:0] _csignals_T_203 = _csignals_T_19 ? 4'h8 : {{1'd0}, _csignals_T_202}; // @[Lookup.scala 34:39]
  wire [3:0] _csignals_T_204 = _csignals_T_17 ? 4'h8 : _csignals_T_203; // @[Lookup.scala 34:39]
  wire [3:0] _csignals_T_205 = _csignals_T_15 ? 4'h8 : _csignals_T_204; // @[Lookup.scala 34:39]
  wire [3:0] _csignals_T_206 = _csignals_T_13 ? 4'h8 : _csignals_T_205; // @[Lookup.scala 34:39]
  wire [3:0] _csignals_T_207 = _csignals_T_11 ? 4'h8 : _csignals_T_206; // @[Lookup.scala 34:39]
  wire [3:0] _csignals_T_208 = _csignals_T_9 ? 4'h8 : _csignals_T_207; // @[Lookup.scala 34:39]
  wire [3:0] _csignals_T_209 = _csignals_T_7 ? 4'h2 : _csignals_T_208; // @[Lookup.scala 34:39]
  wire [5:0] _csignals_T_210 = _csignals_T_5 ? 6'h20 : {{2'd0}, _csignals_T_209}; // @[Lookup.scala 34:39]
  wire [5:0] _csignals_T_211 = _csignals_T_3 ? 6'h10 : _csignals_T_210; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_221 = _csignals_T_123 ? 23'h400000 : 23'h0; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_222 = _csignals_T_121 ? 23'h200000 : _csignals_T_221; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_223 = _csignals_T_119 ? 23'h100000 : _csignals_T_222; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_224 = _csignals_T_117 ? 23'h80000 : _csignals_T_223; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_225 = _csignals_T_115 ? 23'h40000 : _csignals_T_224; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_226 = _csignals_T_113 ? 23'h20000 : _csignals_T_225; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_227 = _csignals_T_111 ? 23'h10000 : _csignals_T_226; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_228 = _csignals_T_109 ? 23'h8000 : _csignals_T_227; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_229 = _csignals_T_107 ? 23'h4000 : _csignals_T_228; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_230 = _csignals_T_105 ? 23'h2000 : _csignals_T_229; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_231 = _csignals_T_103 ? 23'h1000 : _csignals_T_230; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_232 = _csignals_T_101 ? 23'h800 : _csignals_T_231; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_233 = _csignals_T_99 ? 23'h400 : _csignals_T_232; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_234 = _csignals_T_97 ? 23'h200 : _csignals_T_233; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_235 = _csignals_T_95 ? 23'h100 : _csignals_T_234; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_236 = _csignals_T_93 ? 23'h20 : _csignals_T_235; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_237 = _csignals_T_91 ? 23'h2 : _csignals_T_236; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_238 = _csignals_T_89 ? 23'h1 : _csignals_T_237; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_239 = _csignals_T_87 ? 23'h4 : _csignals_T_238; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_240 = _csignals_T_85 ? 23'h8 : _csignals_T_239; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_241 = _csignals_T_83 ? 23'h80 : _csignals_T_240; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_242 = _csignals_T_81 ? 23'h40 : _csignals_T_241; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_243 = _csignals_T_79 ? 23'h10 : _csignals_T_242; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_244 = _csignals_T_77 ? 23'h2 : _csignals_T_243; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_245 = _csignals_T_75 ? 23'h2 : _csignals_T_244; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_246 = _csignals_T_73 ? 23'h20 : _csignals_T_245; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_247 = _csignals_T_71 ? 23'h2 : _csignals_T_246; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_248 = _csignals_T_69 ? 23'h1 : _csignals_T_247; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_249 = _csignals_T_67 ? 23'h200 : _csignals_T_248; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_250 = _csignals_T_65 ? 23'h100 : _csignals_T_249; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_251 = _csignals_T_63 ? 23'h20 : _csignals_T_250; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_252 = _csignals_T_61 ? 23'h1 : _csignals_T_251; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_253 = _csignals_T_59 ? 23'h80 : _csignals_T_252; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_254 = _csignals_T_57 ? 23'h40 : _csignals_T_253; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_255 = _csignals_T_55 ? 23'h20 : _csignals_T_254; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_256 = _csignals_T_53 ? 23'h4 : _csignals_T_255; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_257 = _csignals_T_51 ? 23'h8 : _csignals_T_256; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_258 = _csignals_T_49 ? 23'h10 : _csignals_T_257; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_259 = _csignals_T_47 ? 23'h2 : _csignals_T_258; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_260 = _csignals_T_45 ? 23'h2 : _csignals_T_259; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_261 = _csignals_T_43 ? 23'h1 : _csignals_T_260; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_262 = _csignals_T_41 ? 23'h1 : _csignals_T_261; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_263 = _csignals_T_39 ? 23'h1 : _csignals_T_262; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_264 = _csignals_T_37 ? 23'h1 : _csignals_T_263; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_265 = _csignals_T_35 ? 23'h1 : _csignals_T_264; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_266 = _csignals_T_33 ? 23'h1 : _csignals_T_265; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_267 = _csignals_T_31 ? 23'h1 : _csignals_T_266; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_268 = _csignals_T_29 ? 23'h1 : _csignals_T_267; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_269 = _csignals_T_27 ? 23'h1 : _csignals_T_268; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_270 = _csignals_T_25 ? 23'h1 : _csignals_T_269; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_271 = _csignals_T_23 ? 23'h1 : _csignals_T_270; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_272 = _csignals_T_21 ? 23'h1 : _csignals_T_271; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_273 = _csignals_T_19 ? 23'h2 : _csignals_T_272; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_274 = _csignals_T_17 ? 23'h2 : _csignals_T_273; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_275 = _csignals_T_15 ? 23'h2 : _csignals_T_274; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_276 = _csignals_T_13 ? 23'h2 : _csignals_T_275; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_277 = _csignals_T_11 ? 23'h2 : _csignals_T_276; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_278 = _csignals_T_9 ? 23'h2 : _csignals_T_277; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_279 = _csignals_T_7 ? 23'h1 : _csignals_T_278; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_280 = _csignals_T_5 ? 23'h1 : _csignals_T_279; // @[Lookup.scala 34:39]
  wire [22:0] _csignals_T_281 = _csignals_T_3 ? 23'h1 : _csignals_T_280; // @[Lookup.scala 34:39]
  wire [22:0] alu_op = _csignals_T_1 ? 23'h1 : _csignals_T_281; // @[Lookup.scala 34:39]
  wire  _csignals_T_413 = _csignals_T_19 ? 1'h0 : _csignals_T_21 | (_csignals_T_23 | (_csignals_T_25 | (_csignals_T_27
     | (_csignals_T_29 | (_csignals_T_31 | (_csignals_T_33 | (_csignals_T_35 | (_csignals_T_37 | (_csignals_T_39 | (
    _csignals_T_41 | (_csignals_T_43 | (_csignals_T_45 | (_csignals_T_47 | (_csignals_T_49 | (_csignals_T_51 | (
    _csignals_T_53 | (_csignals_T_55 | (_csignals_T_57 | (_csignals_T_59 | (_csignals_T_61 | (_csignals_T_63 | (
    _csignals_T_65 | _csignals_T_67)))))))))))))))))))))); // @[Lookup.scala 34:39]
  wire  _csignals_T_414 = _csignals_T_17 ? 1'h0 : _csignals_T_413; // @[Lookup.scala 34:39]
  wire  _csignals_T_415 = _csignals_T_15 ? 1'h0 : _csignals_T_414; // @[Lookup.scala 34:39]
  wire  _csignals_T_416 = _csignals_T_13 ? 1'h0 : _csignals_T_415; // @[Lookup.scala 34:39]
  wire  _csignals_T_417 = _csignals_T_11 ? 1'h0 : _csignals_T_416; // @[Lookup.scala 34:39]
  wire  _csignals_T_418 = _csignals_T_9 ? 1'h0 : _csignals_T_417; // @[Lookup.scala 34:39]
  wire  _csignals_T_430 = _csignals_T_125 ? 1'h0 : _csignals_T_127 | (_csignals_T_129 | (_csignals_T_131 | (
    _csignals_T_133 | (_csignals_T_135 | (_csignals_T_137 | (_csignals_T_139 | _csignals_T_141)))))); // @[Lookup.scala 34:39]
  wire  _csignals_T_460 = _csignals_T_65 | (_csignals_T_67 | (_csignals_T_69 | (_csignals_T_71 | (_csignals_T_73 | (
    _csignals_T_75 | (_csignals_T_77 | (_csignals_T_79 | (_csignals_T_81 | (_csignals_T_83 | (_csignals_T_85 | (
    _csignals_T_87 | (_csignals_T_89 | (_csignals_T_91 | (_csignals_T_93 | (_csignals_T_95 | (_csignals_T_97 | (
    _csignals_T_99 | (_csignals_T_101 | (_csignals_T_103 | (_csignals_T_105 | (_csignals_T_107 | (_csignals_T_109 | (
    _csignals_T_111 | (_csignals_T_113 | (_csignals_T_115 | (_csignals_T_117 | (_csignals_T_119 | (_csignals_T_121 | (
    _csignals_T_123 | _csignals_T_430))))))))))))))))))))))))))))); // @[Lookup.scala 34:39]
  wire  _csignals_T_472 = _csignals_T_41 ? 1'h0 : _csignals_T_43 | (_csignals_T_45 | (_csignals_T_47 | (_csignals_T_49
     | (_csignals_T_51 | (_csignals_T_53 | (_csignals_T_55 | (_csignals_T_57 | (_csignals_T_59 | (_csignals_T_61 | (
    _csignals_T_63 | _csignals_T_460)))))))))); // @[Lookup.scala 34:39]
  wire  _csignals_T_473 = _csignals_T_39 ? 1'h0 : _csignals_T_472; // @[Lookup.scala 34:39]
  wire  _csignals_T_474 = _csignals_T_37 ? 1'h0 : _csignals_T_473; // @[Lookup.scala 34:39]
  wire  _csignals_T_475 = _csignals_T_35 ? 1'h0 : _csignals_T_474; // @[Lookup.scala 34:39]
  wire  _csignals_T_483 = _csignals_T_19 ? 1'h0 : _csignals_T_21 | (_csignals_T_23 | (_csignals_T_25 | (_csignals_T_27
     | (_csignals_T_29 | (_csignals_T_31 | (_csignals_T_33 | _csignals_T_475)))))); // @[Lookup.scala 34:39]
  wire  _csignals_T_484 = _csignals_T_17 ? 1'h0 : _csignals_T_483; // @[Lookup.scala 34:39]
  wire  _csignals_T_485 = _csignals_T_15 ? 1'h0 : _csignals_T_484; // @[Lookup.scala 34:39]
  wire  _csignals_T_486 = _csignals_T_13 ? 1'h0 : _csignals_T_485; // @[Lookup.scala 34:39]
  wire  _csignals_T_487 = _csignals_T_11 ? 1'h0 : _csignals_T_486; // @[Lookup.scala 34:39]
  wire  _csignals_T_488 = _csignals_T_9 ? 1'h0 : _csignals_T_487; // @[Lookup.scala 34:39]
  wire  _csignals_T_553 = _csignals_T_19 ? 1'h0 : _csignals_T_21 | (_csignals_T_23 | (_csignals_T_25 | (_csignals_T_27
     | (_csignals_T_29 | (_csignals_T_31 | _csignals_T_33))))); // @[Lookup.scala 34:39]
  wire  _csignals_T_554 = _csignals_T_17 ? 1'h0 : _csignals_T_553; // @[Lookup.scala 34:39]
  wire  _csignals_T_555 = _csignals_T_15 ? 1'h0 : _csignals_T_554; // @[Lookup.scala 34:39]
  wire  _csignals_T_556 = _csignals_T_13 ? 1'h0 : _csignals_T_555; // @[Lookup.scala 34:39]
  wire  _csignals_T_557 = _csignals_T_11 ? 1'h0 : _csignals_T_556; // @[Lookup.scala 34:39]
  wire  _csignals_T_558 = _csignals_T_9 ? 1'h0 : _csignals_T_557; // @[Lookup.scala 34:39]
  wire  _csignals_T_559 = _csignals_T_7 ? 1'h0 : _csignals_T_558; // @[Lookup.scala 34:39]
  wire  _csignals_T_560 = _csignals_T_5 ? 1'h0 : _csignals_T_559; // @[Lookup.scala 34:39]
  wire  _csignals_T_561 = _csignals_T_3 ? 1'h0 : _csignals_T_560; // @[Lookup.scala 34:39]
  wire  _csignals_T_592 = _csignals_T_81 | (_csignals_T_83 | (_csignals_T_85 | (_csignals_T_87 | (_csignals_T_89 | (
    _csignals_T_91 | (_csignals_T_93 | (_csignals_T_95 | (_csignals_T_97 | (_csignals_T_99 | (_csignals_T_101 | (
    _csignals_T_103 | (_csignals_T_105 | (_csignals_T_107 | (_csignals_T_109 | (_csignals_T_111 | (_csignals_T_113 | (
    _csignals_T_115 | (_csignals_T_117 | (_csignals_T_119 | (_csignals_T_121 | (_csignals_T_123 | (_csignals_T_125 | (
    _csignals_T_127 | (_csignals_T_129 | (_csignals_T_131 | (_csignals_T_133 | (_csignals_T_135 | (_csignals_T_137 | (
    _csignals_T_139 | _csignals_T_141))))))))))))))))))))))))))))); // @[Lookup.scala 34:39]
  wire  _csignals_T_593 = _csignals_T_79 | _csignals_T_592; // @[Lookup.scala 34:39]
  wire  _csignals_T_622 = _csignals_T_21 | (_csignals_T_23 | (_csignals_T_25 | (_csignals_T_27 | (_csignals_T_29 | (
    _csignals_T_31 | (_csignals_T_33 | (_csignals_T_35 | (_csignals_T_37 | (_csignals_T_39 | (_csignals_T_41 | (
    _csignals_T_43 | (_csignals_T_45 | (_csignals_T_47 | (_csignals_T_49 | (_csignals_T_51 | (_csignals_T_53 | (
    _csignals_T_55 | (_csignals_T_57 | (_csignals_T_59 | (_csignals_T_61 | (_csignals_T_63 | (_csignals_T_65 | (
    _csignals_T_67 | (_csignals_T_69 | (_csignals_T_71 | (_csignals_T_73 | (_csignals_T_75 | (_csignals_T_77 | (
    _csignals_T_79 | _csignals_T_592))))))))))))))))))))))))))))); // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_623 = _csignals_T_19 ? 7'h40 : {{6'd0}, _csignals_T_622}; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_624 = _csignals_T_17 ? 7'h20 : _csignals_T_623; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_625 = _csignals_T_15 ? 7'h10 : _csignals_T_624; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_626 = _csignals_T_13 ? 7'h8 : _csignals_T_625; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_627 = _csignals_T_11 ? 7'h4 : _csignals_T_626; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_628 = _csignals_T_9 ? 7'h2 : _csignals_T_627; // @[Lookup.scala 34:39]
  wire [8:0] _csignals_T_629 = _csignals_T_7 ? 9'h100 : {{2'd0}, _csignals_T_628}; // @[Lookup.scala 34:39]
  wire [8:0] _csignals_T_630 = _csignals_T_5 ? 9'h80 : _csignals_T_629; // @[Lookup.scala 34:39]
  wire [8:0] _csignals_T_631 = _csignals_T_3 ? 9'h1 : _csignals_T_630; // @[Lookup.scala 34:39]
  wire  _csignals_T_641 = _csignals_T_123 ? 1'h0 : _csignals_T_125; // @[Lookup.scala 34:39]
  wire  _csignals_T_642 = _csignals_T_121 ? 1'h0 : _csignals_T_641; // @[Lookup.scala 34:39]
  wire  _csignals_T_643 = _csignals_T_119 ? 1'h0 : _csignals_T_642; // @[Lookup.scala 34:39]
  wire  _csignals_T_644 = _csignals_T_117 ? 1'h0 : _csignals_T_643; // @[Lookup.scala 34:39]
  wire  _csignals_T_645 = _csignals_T_115 ? 1'h0 : _csignals_T_644; // @[Lookup.scala 34:39]
  wire  _csignals_T_646 = _csignals_T_113 ? 1'h0 : _csignals_T_645; // @[Lookup.scala 34:39]
  wire  _csignals_T_647 = _csignals_T_111 ? 1'h0 : _csignals_T_646; // @[Lookup.scala 34:39]
  wire  _csignals_T_648 = _csignals_T_109 ? 1'h0 : _csignals_T_647; // @[Lookup.scala 34:39]
  wire  _csignals_T_649 = _csignals_T_107 ? 1'h0 : _csignals_T_648; // @[Lookup.scala 34:39]
  wire  _csignals_T_650 = _csignals_T_105 ? 1'h0 : _csignals_T_649; // @[Lookup.scala 34:39]
  wire  _csignals_T_651 = _csignals_T_103 ? 1'h0 : _csignals_T_650; // @[Lookup.scala 34:39]
  wire  _csignals_T_652 = _csignals_T_101 ? 1'h0 : _csignals_T_651; // @[Lookup.scala 34:39]
  wire  _csignals_T_653 = _csignals_T_99 ? 1'h0 : _csignals_T_652; // @[Lookup.scala 34:39]
  wire  _csignals_T_654 = _csignals_T_97 ? 1'h0 : _csignals_T_653; // @[Lookup.scala 34:39]
  wire  _csignals_T_655 = _csignals_T_95 ? 1'h0 : _csignals_T_654; // @[Lookup.scala 34:39]
  wire  _csignals_T_656 = _csignals_T_93 ? 1'h0 : _csignals_T_655; // @[Lookup.scala 34:39]
  wire  _csignals_T_657 = _csignals_T_91 ? 1'h0 : _csignals_T_656; // @[Lookup.scala 34:39]
  wire  _csignals_T_658 = _csignals_T_89 ? 1'h0 : _csignals_T_657; // @[Lookup.scala 34:39]
  wire  _csignals_T_659 = _csignals_T_87 ? 1'h0 : _csignals_T_658; // @[Lookup.scala 34:39]
  wire  _csignals_T_660 = _csignals_T_85 ? 1'h0 : _csignals_T_659; // @[Lookup.scala 34:39]
  wire  _csignals_T_661 = _csignals_T_83 ? 1'h0 : _csignals_T_660; // @[Lookup.scala 34:39]
  wire  _csignals_T_662 = _csignals_T_81 ? 1'h0 : _csignals_T_661; // @[Lookup.scala 34:39]
  wire  _csignals_T_663 = _csignals_T_79 ? 1'h0 : _csignals_T_662; // @[Lookup.scala 34:39]
  wire  _csignals_T_664 = _csignals_T_77 ? 1'h0 : _csignals_T_663; // @[Lookup.scala 34:39]
  wire  _csignals_T_665 = _csignals_T_75 ? 1'h0 : _csignals_T_664; // @[Lookup.scala 34:39]
  wire  _csignals_T_666 = _csignals_T_73 ? 1'h0 : _csignals_T_665; // @[Lookup.scala 34:39]
  wire  _csignals_T_667 = _csignals_T_71 ? 1'h0 : _csignals_T_666; // @[Lookup.scala 34:39]
  wire  _csignals_T_668 = _csignals_T_69 ? 1'h0 : _csignals_T_667; // @[Lookup.scala 34:39]
  wire  _csignals_T_669 = _csignals_T_67 ? 1'h0 : _csignals_T_668; // @[Lookup.scala 34:39]
  wire  _csignals_T_670 = _csignals_T_65 ? 1'h0 : _csignals_T_669; // @[Lookup.scala 34:39]
  wire  _csignals_T_671 = _csignals_T_63 ? 1'h0 : _csignals_T_670; // @[Lookup.scala 34:39]
  wire  _csignals_T_672 = _csignals_T_61 ? 1'h0 : _csignals_T_671; // @[Lookup.scala 34:39]
  wire  _csignals_T_673 = _csignals_T_59 ? 1'h0 : _csignals_T_672; // @[Lookup.scala 34:39]
  wire  _csignals_T_674 = _csignals_T_57 ? 1'h0 : _csignals_T_673; // @[Lookup.scala 34:39]
  wire  _csignals_T_675 = _csignals_T_55 ? 1'h0 : _csignals_T_674; // @[Lookup.scala 34:39]
  wire  _csignals_T_676 = _csignals_T_53 ? 1'h0 : _csignals_T_675; // @[Lookup.scala 34:39]
  wire  _csignals_T_677 = _csignals_T_51 ? 1'h0 : _csignals_T_676; // @[Lookup.scala 34:39]
  wire  _csignals_T_678 = _csignals_T_49 ? 1'h0 : _csignals_T_677; // @[Lookup.scala 34:39]
  wire  _csignals_T_679 = _csignals_T_47 ? 1'h0 : _csignals_T_678; // @[Lookup.scala 34:39]
  wire  _csignals_T_680 = _csignals_T_45 ? 1'h0 : _csignals_T_679; // @[Lookup.scala 34:39]
  wire  _csignals_T_681 = _csignals_T_43 ? 1'h0 : _csignals_T_680; // @[Lookup.scala 34:39]
  wire  _csignals_T_693 = _csignals_T_19 ? 1'h0 : _csignals_T_21 | (_csignals_T_23 | (_csignals_T_25 | (_csignals_T_27
     | (_csignals_T_29 | (_csignals_T_31 | (_csignals_T_33 | (_csignals_T_35 | (_csignals_T_37 | (_csignals_T_39 | (
    _csignals_T_41 | _csignals_T_681)))))))))); // @[Lookup.scala 34:39]
  wire  _csignals_T_694 = _csignals_T_17 ? 1'h0 : _csignals_T_693; // @[Lookup.scala 34:39]
  wire  _csignals_T_695 = _csignals_T_15 ? 1'h0 : _csignals_T_694; // @[Lookup.scala 34:39]
  wire  _csignals_T_696 = _csignals_T_13 ? 1'h0 : _csignals_T_695; // @[Lookup.scala 34:39]
  wire  _csignals_T_697 = _csignals_T_11 ? 1'h0 : _csignals_T_696; // @[Lookup.scala 34:39]
  wire  _csignals_T_698 = _csignals_T_9 ? 1'h0 : _csignals_T_697; // @[Lookup.scala 34:39]
  wire  _csignals_T_699 = _csignals_T_7 ? 1'h0 : _csignals_T_698; // @[Lookup.scala 34:39]
  wire  _csignals_T_700 = _csignals_T_5 ? 1'h0 : _csignals_T_699; // @[Lookup.scala 34:39]
  wire  _csignals_T_701 = _csignals_T_3 ? 1'h0 : _csignals_T_700; // @[Lookup.scala 34:39]
  wire  _csignals_T_756 = _csignals_T_33 ? 1'h0 : _csignals_T_35 | (_csignals_T_37 | (_csignals_T_39 | _csignals_T_41)); // @[Lookup.scala 34:39]
  wire  _csignals_T_757 = _csignals_T_31 ? 1'h0 : _csignals_T_756; // @[Lookup.scala 34:39]
  wire  _csignals_T_758 = _csignals_T_29 ? 1'h0 : _csignals_T_757; // @[Lookup.scala 34:39]
  wire  _csignals_T_759 = _csignals_T_27 ? 1'h0 : _csignals_T_758; // @[Lookup.scala 34:39]
  wire  _csignals_T_760 = _csignals_T_25 ? 1'h0 : _csignals_T_759; // @[Lookup.scala 34:39]
  wire  _csignals_T_761 = _csignals_T_23 ? 1'h0 : _csignals_T_760; // @[Lookup.scala 34:39]
  wire  _csignals_T_762 = _csignals_T_21 ? 1'h0 : _csignals_T_761; // @[Lookup.scala 34:39]
  wire  _csignals_T_763 = _csignals_T_19 ? 1'h0 : _csignals_T_762; // @[Lookup.scala 34:39]
  wire  _csignals_T_764 = _csignals_T_17 ? 1'h0 : _csignals_T_763; // @[Lookup.scala 34:39]
  wire  _csignals_T_765 = _csignals_T_15 ? 1'h0 : _csignals_T_764; // @[Lookup.scala 34:39]
  wire  _csignals_T_766 = _csignals_T_13 ? 1'h0 : _csignals_T_765; // @[Lookup.scala 34:39]
  wire  _csignals_T_767 = _csignals_T_11 ? 1'h0 : _csignals_T_766; // @[Lookup.scala 34:39]
  wire  _csignals_T_768 = _csignals_T_9 ? 1'h0 : _csignals_T_767; // @[Lookup.scala 34:39]
  wire  _csignals_T_769 = _csignals_T_7 ? 1'h0 : _csignals_T_768; // @[Lookup.scala 34:39]
  wire  _csignals_T_770 = _csignals_T_5 ? 1'h0 : _csignals_T_769; // @[Lookup.scala 34:39]
  wire  _csignals_T_771 = _csignals_T_3 ? 1'h0 : _csignals_T_770; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_822 = _csignals_T_41 ? 7'h40 : 7'h0; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_823 = _csignals_T_39 ? 7'h4 : _csignals_T_822; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_824 = _csignals_T_37 ? 7'h2 : _csignals_T_823; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_825 = _csignals_T_35 ? 7'h1 : _csignals_T_824; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_826 = _csignals_T_33 ? 7'h40 : _csignals_T_825; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_827 = _csignals_T_31 ? 7'h20 : _csignals_T_826; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_828 = _csignals_T_29 ? 7'h10 : _csignals_T_827; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_829 = _csignals_T_27 ? 7'h8 : _csignals_T_828; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_830 = _csignals_T_25 ? 7'h4 : _csignals_T_829; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_831 = _csignals_T_23 ? 7'h2 : _csignals_T_830; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_832 = _csignals_T_21 ? 7'h1 : _csignals_T_831; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_833 = _csignals_T_19 ? 7'h0 : _csignals_T_832; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_834 = _csignals_T_17 ? 7'h0 : _csignals_T_833; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_835 = _csignals_T_15 ? 7'h0 : _csignals_T_834; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_836 = _csignals_T_13 ? 7'h0 : _csignals_T_835; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_837 = _csignals_T_11 ? 7'h0 : _csignals_T_836; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_838 = _csignals_T_9 ? 7'h0 : _csignals_T_837; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_839 = _csignals_T_7 ? 7'h0 : _csignals_T_838; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_840 = _csignals_T_5 ? 7'h0 : _csignals_T_839; // @[Lookup.scala 34:39]
  wire [6:0] _csignals_T_841 = _csignals_T_3 ? 7'h0 : _csignals_T_840; // @[Lookup.scala 34:39]
  wire  _csignals_T_853 = _csignals_T_119 ? 1'h0 : _csignals_T_121 | (_csignals_T_123 | _csignals_T_430); // @[Lookup.scala 34:39]
  wire  _csignals_T_854 = _csignals_T_117 ? 1'h0 : _csignals_T_853; // @[Lookup.scala 34:39]
  wire  _csignals_T_857 = _csignals_T_111 ? 1'h0 : _csignals_T_113 | (_csignals_T_115 | _csignals_T_854); // @[Lookup.scala 34:39]
  wire  _csignals_T_858 = _csignals_T_109 ? 1'h0 : _csignals_T_857; // @[Lookup.scala 34:39]
  wire  _csignals_T_860 = _csignals_T_105 ? 1'h0 : _csignals_T_107 | _csignals_T_858; // @[Lookup.scala 34:39]
  wire  _csignals_T_861 = _csignals_T_103 ? 1'h0 : _csignals_T_860; // @[Lookup.scala 34:39]
  wire  _csignals_T_862 = _csignals_T_101 ? 1'h0 : _csignals_T_861; // @[Lookup.scala 34:39]
  wire  _csignals_T_863 = _csignals_T_99 ? 1'h0 : _csignals_T_862; // @[Lookup.scala 34:39]
  wire  _csignals_T_869 = _csignals_T_87 ? 1'h0 : _csignals_T_89 | (_csignals_T_91 | (_csignals_T_93 | (_csignals_T_95
     | (_csignals_T_97 | _csignals_T_863)))); // @[Lookup.scala 34:39]
  wire  _csignals_T_870 = _csignals_T_85 ? 1'h0 : _csignals_T_869; // @[Lookup.scala 34:39]
  wire  _csignals_T_871 = _csignals_T_83 ? 1'h0 : _csignals_T_870; // @[Lookup.scala 34:39]
  wire  _csignals_T_872 = _csignals_T_81 ? 1'h0 : _csignals_T_871; // @[Lookup.scala 34:39]
  wire  _csignals_T_873 = _csignals_T_79 ? 1'h0 : _csignals_T_872; // @[Lookup.scala 34:39]
  wire  _csignals_T_874 = _csignals_T_77 ? 1'h0 : _csignals_T_873; // @[Lookup.scala 34:39]
  wire  _csignals_T_875 = _csignals_T_75 ? 1'h0 : _csignals_T_874; // @[Lookup.scala 34:39]
  wire  _csignals_T_876 = _csignals_T_73 ? 1'h0 : _csignals_T_875; // @[Lookup.scala 34:39]
  wire  _csignals_T_877 = _csignals_T_71 ? 1'h0 : _csignals_T_876; // @[Lookup.scala 34:39]
  wire  _csignals_T_878 = _csignals_T_69 ? 1'h0 : _csignals_T_877; // @[Lookup.scala 34:39]
  wire  _csignals_T_883 = _csignals_T_59 ? 1'h0 : _csignals_T_61 | (_csignals_T_63 | (_csignals_T_65 | (_csignals_T_67
     | _csignals_T_878))); // @[Lookup.scala 34:39]
  wire  _csignals_T_884 = _csignals_T_57 ? 1'h0 : _csignals_T_883; // @[Lookup.scala 34:39]
  wire  _csignals_T_885 = _csignals_T_55 ? 1'h0 : _csignals_T_884; // @[Lookup.scala 34:39]
  wire  _csignals_T_886 = _csignals_T_53 ? 1'h0 : _csignals_T_885; // @[Lookup.scala 34:39]
  wire  _csignals_T_887 = _csignals_T_51 ? 1'h0 : _csignals_T_886; // @[Lookup.scala 34:39]
  wire  _csignals_T_888 = _csignals_T_49 ? 1'h0 : _csignals_T_887; // @[Lookup.scala 34:39]
  wire  _csignals_T_889 = _csignals_T_47 ? 1'h0 : _csignals_T_888; // @[Lookup.scala 34:39]
  wire  _csignals_T_890 = _csignals_T_45 ? 1'h0 : _csignals_T_889; // @[Lookup.scala 34:39]
  wire  _csignals_T_891 = _csignals_T_43 ? 1'h0 : _csignals_T_890; // @[Lookup.scala 34:39]
  wire  _csignals_T_892 = _csignals_T_41 ? 1'h0 : _csignals_T_891; // @[Lookup.scala 34:39]
  wire  _csignals_T_893 = _csignals_T_39 ? 1'h0 : _csignals_T_892; // @[Lookup.scala 34:39]
  wire  _csignals_T_894 = _csignals_T_37 ? 1'h0 : _csignals_T_893; // @[Lookup.scala 34:39]
  wire  _csignals_T_895 = _csignals_T_35 ? 1'h0 : _csignals_T_894; // @[Lookup.scala 34:39]
  wire  _csignals_T_896 = _csignals_T_33 ? 1'h0 : _csignals_T_895; // @[Lookup.scala 34:39]
  wire  _csignals_T_897 = _csignals_T_31 ? 1'h0 : _csignals_T_896; // @[Lookup.scala 34:39]
  wire  _csignals_T_898 = _csignals_T_29 ? 1'h0 : _csignals_T_897; // @[Lookup.scala 34:39]
  wire  _csignals_T_899 = _csignals_T_27 ? 1'h0 : _csignals_T_898; // @[Lookup.scala 34:39]
  wire  _csignals_T_900 = _csignals_T_25 ? 1'h0 : _csignals_T_899; // @[Lookup.scala 34:39]
  wire  _csignals_T_901 = _csignals_T_23 ? 1'h0 : _csignals_T_900; // @[Lookup.scala 34:39]
  wire  _csignals_T_902 = _csignals_T_21 ? 1'h0 : _csignals_T_901; // @[Lookup.scala 34:39]
  wire  _csignals_T_903 = _csignals_T_19 ? 1'h0 : _csignals_T_902; // @[Lookup.scala 34:39]
  wire  _csignals_T_904 = _csignals_T_17 ? 1'h0 : _csignals_T_903; // @[Lookup.scala 34:39]
  wire  _csignals_T_905 = _csignals_T_15 ? 1'h0 : _csignals_T_904; // @[Lookup.scala 34:39]
  wire  _csignals_T_906 = _csignals_T_13 ? 1'h0 : _csignals_T_905; // @[Lookup.scala 34:39]
  wire  _csignals_T_907 = _csignals_T_11 ? 1'h0 : _csignals_T_906; // @[Lookup.scala 34:39]
  wire  _csignals_T_908 = _csignals_T_9 ? 1'h0 : _csignals_T_907; // @[Lookup.scala 34:39]
  wire  _csignals_T_909 = _csignals_T_7 ? 1'h0 : _csignals_T_908; // @[Lookup.scala 34:39]
  wire  _csignals_T_910 = _csignals_T_5 ? 1'h0 : _csignals_T_909; // @[Lookup.scala 34:39]
  wire  _csignals_T_911 = _csignals_T_3 ? 1'h0 : _csignals_T_910; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_944 = _csignals_T_77 ? 3'h4 : {{2'd0}, _csignals_T_593}; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_945 = _csignals_T_75 ? 3'h2 : _csignals_T_944; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_946 = _csignals_T_73 ? 3'h1 : _csignals_T_945; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_947 = _csignals_T_71 ? 3'h1 : _csignals_T_946; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_948 = _csignals_T_69 ? 3'h1 : _csignals_T_947; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_949 = _csignals_T_67 ? 3'h1 : _csignals_T_948; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_950 = _csignals_T_65 ? 3'h1 : _csignals_T_949; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_951 = _csignals_T_63 ? 3'h1 : _csignals_T_950; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_952 = _csignals_T_61 ? 3'h1 : _csignals_T_951; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_953 = _csignals_T_59 ? 3'h1 : _csignals_T_952; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_954 = _csignals_T_57 ? 3'h1 : _csignals_T_953; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_955 = _csignals_T_55 ? 3'h1 : _csignals_T_954; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_956 = _csignals_T_53 ? 3'h1 : _csignals_T_955; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_957 = _csignals_T_51 ? 3'h1 : _csignals_T_956; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_958 = _csignals_T_49 ? 3'h1 : _csignals_T_957; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_959 = _csignals_T_47 ? 3'h4 : _csignals_T_958; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_960 = _csignals_T_45 ? 3'h2 : _csignals_T_959; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_961 = _csignals_T_43 ? 3'h1 : _csignals_T_960; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_962 = _csignals_T_41 ? 3'h1 : _csignals_T_961; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_963 = _csignals_T_39 ? 3'h1 : _csignals_T_962; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_964 = _csignals_T_37 ? 3'h1 : _csignals_T_963; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_965 = _csignals_T_35 ? 3'h1 : _csignals_T_964; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_966 = _csignals_T_33 ? 3'h1 : _csignals_T_965; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_967 = _csignals_T_31 ? 3'h1 : _csignals_T_966; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_968 = _csignals_T_29 ? 3'h1 : _csignals_T_967; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_969 = _csignals_T_27 ? 3'h1 : _csignals_T_968; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_970 = _csignals_T_25 ? 3'h1 : _csignals_T_969; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_971 = _csignals_T_23 ? 3'h1 : _csignals_T_970; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_972 = _csignals_T_21 ? 3'h1 : _csignals_T_971; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_973 = _csignals_T_19 ? 3'h1 : _csignals_T_972; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_974 = _csignals_T_17 ? 3'h1 : _csignals_T_973; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_975 = _csignals_T_15 ? 3'h1 : _csignals_T_974; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_976 = _csignals_T_13 ? 3'h1 : _csignals_T_975; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_977 = _csignals_T_11 ? 3'h1 : _csignals_T_976; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_978 = _csignals_T_9 ? 3'h1 : _csignals_T_977; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_979 = _csignals_T_7 ? 3'h1 : _csignals_T_978; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_980 = _csignals_T_5 ? 3'h1 : _csignals_T_979; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_981 = _csignals_T_3 ? 3'h1 : _csignals_T_980; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_984 = _csignals_T_137 ? 3'h4 : 3'h0; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_985 = _csignals_T_135 ? 3'h2 : _csignals_T_984; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_986 = _csignals_T_133 ? 3'h1 : _csignals_T_985; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_987 = _csignals_T_131 ? 3'h4 : _csignals_T_986; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_988 = _csignals_T_129 ? 3'h2 : _csignals_T_987; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_989 = _csignals_T_127 ? 3'h1 : _csignals_T_988; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_990 = _csignals_T_125 ? 3'h0 : _csignals_T_989; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_991 = _csignals_T_123 ? 3'h0 : _csignals_T_990; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_992 = _csignals_T_121 ? 3'h0 : _csignals_T_991; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_993 = _csignals_T_119 ? 3'h0 : _csignals_T_992; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_994 = _csignals_T_117 ? 3'h0 : _csignals_T_993; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_995 = _csignals_T_115 ? 3'h0 : _csignals_T_994; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_996 = _csignals_T_113 ? 3'h0 : _csignals_T_995; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_997 = _csignals_T_111 ? 3'h0 : _csignals_T_996; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_998 = _csignals_T_109 ? 3'h0 : _csignals_T_997; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_999 = _csignals_T_107 ? 3'h0 : _csignals_T_998; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1000 = _csignals_T_105 ? 3'h0 : _csignals_T_999; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1001 = _csignals_T_103 ? 3'h0 : _csignals_T_1000; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1002 = _csignals_T_101 ? 3'h0 : _csignals_T_1001; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1003 = _csignals_T_99 ? 3'h0 : _csignals_T_1002; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1004 = _csignals_T_97 ? 3'h0 : _csignals_T_1003; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1005 = _csignals_T_95 ? 3'h0 : _csignals_T_1004; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1006 = _csignals_T_93 ? 3'h0 : _csignals_T_1005; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1007 = _csignals_T_91 ? 3'h0 : _csignals_T_1006; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1008 = _csignals_T_89 ? 3'h0 : _csignals_T_1007; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1009 = _csignals_T_87 ? 3'h0 : _csignals_T_1008; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1010 = _csignals_T_85 ? 3'h0 : _csignals_T_1009; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1011 = _csignals_T_83 ? 3'h0 : _csignals_T_1010; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1012 = _csignals_T_81 ? 3'h0 : _csignals_T_1011; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1013 = _csignals_T_79 ? 3'h0 : _csignals_T_1012; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1014 = _csignals_T_77 ? 3'h0 : _csignals_T_1013; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1015 = _csignals_T_75 ? 3'h0 : _csignals_T_1014; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1016 = _csignals_T_73 ? 3'h0 : _csignals_T_1015; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1017 = _csignals_T_71 ? 3'h0 : _csignals_T_1016; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1018 = _csignals_T_69 ? 3'h0 : _csignals_T_1017; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1019 = _csignals_T_67 ? 3'h0 : _csignals_T_1018; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1020 = _csignals_T_65 ? 3'h0 : _csignals_T_1019; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1021 = _csignals_T_63 ? 3'h0 : _csignals_T_1020; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1022 = _csignals_T_61 ? 3'h0 : _csignals_T_1021; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1023 = _csignals_T_59 ? 3'h0 : _csignals_T_1022; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1024 = _csignals_T_57 ? 3'h0 : _csignals_T_1023; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1025 = _csignals_T_55 ? 3'h0 : _csignals_T_1024; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1026 = _csignals_T_53 ? 3'h0 : _csignals_T_1025; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1027 = _csignals_T_51 ? 3'h0 : _csignals_T_1026; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1028 = _csignals_T_49 ? 3'h0 : _csignals_T_1027; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1029 = _csignals_T_47 ? 3'h0 : _csignals_T_1028; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1030 = _csignals_T_45 ? 3'h0 : _csignals_T_1029; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1031 = _csignals_T_43 ? 3'h0 : _csignals_T_1030; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1032 = _csignals_T_41 ? 3'h0 : _csignals_T_1031; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1033 = _csignals_T_39 ? 3'h0 : _csignals_T_1032; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1034 = _csignals_T_37 ? 3'h0 : _csignals_T_1033; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1035 = _csignals_T_35 ? 3'h0 : _csignals_T_1034; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1036 = _csignals_T_33 ? 3'h0 : _csignals_T_1035; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1037 = _csignals_T_31 ? 3'h0 : _csignals_T_1036; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1038 = _csignals_T_29 ? 3'h0 : _csignals_T_1037; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1039 = _csignals_T_27 ? 3'h0 : _csignals_T_1038; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1040 = _csignals_T_25 ? 3'h0 : _csignals_T_1039; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1041 = _csignals_T_23 ? 3'h0 : _csignals_T_1040; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1042 = _csignals_T_21 ? 3'h0 : _csignals_T_1041; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1043 = _csignals_T_19 ? 3'h0 : _csignals_T_1042; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1044 = _csignals_T_17 ? 3'h0 : _csignals_T_1043; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1045 = _csignals_T_15 ? 3'h0 : _csignals_T_1044; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1046 = _csignals_T_13 ? 3'h0 : _csignals_T_1045; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1047 = _csignals_T_11 ? 3'h0 : _csignals_T_1046; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1048 = _csignals_T_9 ? 3'h0 : _csignals_T_1047; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1049 = _csignals_T_7 ? 3'h0 : _csignals_T_1048; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1050 = _csignals_T_5 ? 3'h0 : _csignals_T_1049; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1051 = _csignals_T_3 ? 3'h0 : _csignals_T_1050; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_1052 = _csignals_T_141 ? 2'h2 : 2'h0; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_1053 = _csignals_T_139 ? 2'h1 : _csignals_T_1052; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_1054 = _csignals_T_137 ? 2'h0 : _csignals_T_1053; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_1055 = _csignals_T_135 ? 2'h0 : _csignals_T_1054; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_1056 = _csignals_T_133 ? 2'h0 : _csignals_T_1055; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_1057 = _csignals_T_131 ? 2'h0 : _csignals_T_1056; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_1058 = _csignals_T_129 ? 2'h0 : _csignals_T_1057; // @[Lookup.scala 34:39]
  wire [1:0] _csignals_T_1059 = _csignals_T_127 ? 2'h0 : _csignals_T_1058; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1060 = _csignals_T_125 ? 3'h4 : {{1'd0}, _csignals_T_1059}; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1061 = _csignals_T_123 ? 3'h0 : _csignals_T_1060; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1062 = _csignals_T_121 ? 3'h0 : _csignals_T_1061; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1063 = _csignals_T_119 ? 3'h0 : _csignals_T_1062; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1064 = _csignals_T_117 ? 3'h0 : _csignals_T_1063; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1065 = _csignals_T_115 ? 3'h0 : _csignals_T_1064; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1066 = _csignals_T_113 ? 3'h0 : _csignals_T_1065; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1067 = _csignals_T_111 ? 3'h0 : _csignals_T_1066; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1068 = _csignals_T_109 ? 3'h0 : _csignals_T_1067; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1069 = _csignals_T_107 ? 3'h0 : _csignals_T_1068; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1070 = _csignals_T_105 ? 3'h0 : _csignals_T_1069; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1071 = _csignals_T_103 ? 3'h0 : _csignals_T_1070; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1072 = _csignals_T_101 ? 3'h0 : _csignals_T_1071; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1073 = _csignals_T_99 ? 3'h0 : _csignals_T_1072; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1074 = _csignals_T_97 ? 3'h0 : _csignals_T_1073; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1075 = _csignals_T_95 ? 3'h0 : _csignals_T_1074; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1076 = _csignals_T_93 ? 3'h0 : _csignals_T_1075; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1077 = _csignals_T_91 ? 3'h0 : _csignals_T_1076; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1078 = _csignals_T_89 ? 3'h0 : _csignals_T_1077; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1079 = _csignals_T_87 ? 3'h0 : _csignals_T_1078; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1080 = _csignals_T_85 ? 3'h0 : _csignals_T_1079; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1081 = _csignals_T_83 ? 3'h0 : _csignals_T_1080; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1082 = _csignals_T_81 ? 3'h0 : _csignals_T_1081; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1083 = _csignals_T_79 ? 3'h0 : _csignals_T_1082; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1084 = _csignals_T_77 ? 3'h0 : _csignals_T_1083; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1085 = _csignals_T_75 ? 3'h0 : _csignals_T_1084; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1086 = _csignals_T_73 ? 3'h0 : _csignals_T_1085; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1087 = _csignals_T_71 ? 3'h0 : _csignals_T_1086; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1088 = _csignals_T_69 ? 3'h0 : _csignals_T_1087; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1089 = _csignals_T_67 ? 3'h0 : _csignals_T_1088; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1090 = _csignals_T_65 ? 3'h0 : _csignals_T_1089; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1091 = _csignals_T_63 ? 3'h0 : _csignals_T_1090; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1092 = _csignals_T_61 ? 3'h0 : _csignals_T_1091; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1093 = _csignals_T_59 ? 3'h0 : _csignals_T_1092; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1094 = _csignals_T_57 ? 3'h0 : _csignals_T_1093; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1095 = _csignals_T_55 ? 3'h0 : _csignals_T_1094; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1096 = _csignals_T_53 ? 3'h0 : _csignals_T_1095; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1097 = _csignals_T_51 ? 3'h0 : _csignals_T_1096; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1098 = _csignals_T_49 ? 3'h0 : _csignals_T_1097; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1099 = _csignals_T_47 ? 3'h0 : _csignals_T_1098; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1100 = _csignals_T_45 ? 3'h0 : _csignals_T_1099; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1101 = _csignals_T_43 ? 3'h0 : _csignals_T_1100; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1102 = _csignals_T_41 ? 3'h0 : _csignals_T_1101; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1103 = _csignals_T_39 ? 3'h0 : _csignals_T_1102; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1104 = _csignals_T_37 ? 3'h0 : _csignals_T_1103; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1105 = _csignals_T_35 ? 3'h0 : _csignals_T_1104; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1106 = _csignals_T_33 ? 3'h0 : _csignals_T_1105; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1107 = _csignals_T_31 ? 3'h0 : _csignals_T_1106; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1108 = _csignals_T_29 ? 3'h0 : _csignals_T_1107; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1109 = _csignals_T_27 ? 3'h0 : _csignals_T_1108; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1110 = _csignals_T_25 ? 3'h0 : _csignals_T_1109; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1111 = _csignals_T_23 ? 3'h0 : _csignals_T_1110; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1112 = _csignals_T_21 ? 3'h0 : _csignals_T_1111; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1113 = _csignals_T_19 ? 3'h0 : _csignals_T_1112; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1114 = _csignals_T_17 ? 3'h0 : _csignals_T_1113; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1115 = _csignals_T_15 ? 3'h0 : _csignals_T_1114; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1116 = _csignals_T_13 ? 3'h0 : _csignals_T_1115; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1117 = _csignals_T_11 ? 3'h0 : _csignals_T_1116; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1118 = _csignals_T_9 ? 3'h0 : _csignals_T_1117; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1119 = _csignals_T_7 ? 3'h0 : _csignals_T_1118; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1120 = _csignals_T_5 ? 3'h0 : _csignals_T_1119; // @[Lookup.scala 34:39]
  wire [2:0] _csignals_T_1121 = _csignals_T_3 ? 3'h0 : _csignals_T_1120; // @[Lookup.scala 34:39]
  assign io_inst_type = _csignals_T_1 ? 6'h10 : _csignals_T_211; // @[Lookup.scala 34:39]
  assign io_alu_op = _csignals_T_1 ? 23'h1 : _csignals_T_281; // @[Lookup.scala 34:39]
  assign io_src1_sel = _csignals_T_1 ? 1'h0 : _csignals_T_3 | _csignals_T_5; // @[Lookup.scala 34:39]
  assign io_src2_sel = _csignals_T_1 | (_csignals_T_3 | (_csignals_T_5 | (_csignals_T_7 | _csignals_T_418))); // @[Lookup.scala 34:39]
  assign io_rf_we = _csignals_T_1 | (_csignals_T_3 | (_csignals_T_5 | (_csignals_T_7 | _csignals_T_488))); // @[Lookup.scala 34:39]
  assign io_wb_sel = _csignals_T_1 ? 1'h0 : _csignals_T_561; // @[Lookup.scala 34:39]
  assign io_br_type = _csignals_T_1 ? 9'h1 : _csignals_T_631; // @[Lookup.scala 34:39]
  assign io_mem_en = _csignals_T_1 ? 1'h0 : _csignals_T_701; // @[Lookup.scala 34:39]
  assign io_mem_wr = _csignals_T_1 ? 1'h0 : _csignals_T_771; // @[Lookup.scala 34:39]
  assign io_mem_type = _csignals_T_1 ? 7'h0 : _csignals_T_841; // @[Lookup.scala 34:39]
  assign io_rv64w = _csignals_T_1 ? 1'h0 : _csignals_T_911; // @[Lookup.scala 34:39]
  assign io_ex_sel = _csignals_T_1 ? 3'h1 : _csignals_T_981; // @[Lookup.scala 34:39]
  assign io_csr_op = _csignals_T_1 ? 3'h0 : _csignals_T_1051; // @[Lookup.scala 34:39]
  assign io_exc_type = _csignals_T_1 ? 3'h0 : _csignals_T_1121; // @[Lookup.scala 34:39]
  assign io_op_muldiv = |alu_op[22:10]; // @[Id_stage.scala 264:40]
endmodule
module ysyx_22051110_RegFile(
  input         clock,
  input         reset,
  input  [4:0]  io_raddr1,
  input  [4:0]  io_raddr2,
  input  [4:0]  io_waddr,
  input  [63:0] io_wdata,
  input         io_wen,
  output [63:0] io_rdata1,
  output [63:0] io_rdata2
);
  wire  my_gpr_clock; // @[RegFile.scala 35:24]
  wire  my_gpr_reset; // @[RegFile.scala 35:24]
  wire [4:0] my_gpr_raddr1; // @[RegFile.scala 35:24]
  wire [4:0] my_gpr_raddr2; // @[RegFile.scala 35:24]
  wire [4:0] my_gpr_waddr; // @[RegFile.scala 35:24]
  wire [63:0] my_gpr_wdata; // @[RegFile.scala 35:24]
  wire  my_gpr_wen; // @[RegFile.scala 35:24]
  wire [63:0] my_gpr_rdata1; // @[RegFile.scala 35:24]
  wire [63:0] my_gpr_rdata2; // @[RegFile.scala 35:24]
  ysyx_22051110_RegFileV my_gpr ( // @[RegFile.scala 35:24]
    .clock(my_gpr_clock),
    .reset(my_gpr_reset),
    .raddr1(my_gpr_raddr1),
    .raddr2(my_gpr_raddr2),
    .waddr(my_gpr_waddr),
    .wdata(my_gpr_wdata),
    .wen(my_gpr_wen),
    .rdata1(my_gpr_rdata1),
    .rdata2(my_gpr_rdata2)
  );
  assign io_rdata1 = my_gpr_rdata1; // @[RegFile.scala 43:15]
  assign io_rdata2 = my_gpr_rdata2; // @[RegFile.scala 44:15]
  assign my_gpr_clock = clock; // @[RegFile.scala 36:21]
  assign my_gpr_reset = reset; // @[RegFile.scala 37:21]
  assign my_gpr_raddr1 = io_raddr1; // @[RegFile.scala 38:22]
  assign my_gpr_raddr2 = io_raddr2; // @[RegFile.scala 39:22]
  assign my_gpr_waddr = io_waddr; // @[RegFile.scala 40:21]
  assign my_gpr_wdata = io_wdata; // @[RegFile.scala 41:21]
  assign my_gpr_wen = io_wen; // @[RegFile.scala 42:19]
endmodule
module ysyx_22051110_Id_stage(
  input         clock,
  input         reset,
  output        io_if2id_ready,
  input         io_if2id_valid,
  input  [31:0] io_if2id_bits_inst,
  input  [31:0] io_if2id_bits_pc,
  input         io_id2ex_ready,
  output        io_id2ex_valid,
  output [22:0] io_id2ex_bits_alu_op,
  output        io_id2ex_bits_src1_sel,
  output        io_id2ex_bits_src2_sel,
  output [8:0]  io_id2ex_bits_br_type,
  output        io_id2ex_bits_gr_we,
  output        io_id2ex_bits_wb_sel,
  output        io_id2ex_bits_mem_en,
  output        io_id2ex_bits_mem_wr,
  output [6:0]  io_id2ex_bits_mem_type,
  output        io_id2ex_bits_rv64w,
  output [2:0]  io_id2ex_bits_ex_sel,
  output [2:0]  io_id2ex_bits_csr_op,
  output [2:0]  io_id2ex_bits_exc_type,
  output        io_id2ex_bits_op_muldiv,
  output        io_id2ex_bits_is_fencei,
  output [4:0]  io_id2ex_bits_dest,
  output [31:0] io_id2ex_bits_pc,
  output [63:0] io_id2ex_bits_rs1,
  output [63:0] io_id2ex_bits_rs2,
  output [63:0] io_id2ex_bits_imm,
  output [63:0] io_id2ex_bits_mem_wdata,
  output [11:0] io_id2ex_bits_csr_num,
  input         io_wb2rf_rf_we,
  input  [4:0]  io_wb2rf_waddr,
  input  [63:0] io_wb2rf_wdata,
  input         io_exc_flush,
  input         io_br_flush,
  input         io_es_forward_valid,
  input         io_es_forward_bits_en,
  input  [4:0]  io_es_forward_bits_dest,
  input  [63:0] io_es_forward_bits_data,
  input         io_ms_forward_valid,
  input         io_ms_forward_bits_en,
  input  [4:0]  io_ms_forward_bits_dest,
  input  [63:0] io_ms_forward_bits_data,
  input         io_ws_forward_valid,
  input         io_ws_forward_bits_en,
  input  [4:0]  io_ws_forward_bits_dest,
  input  [63:0] io_ws_forward_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] my_decoder_io_inst; // @[Id_stage.scala 294:32]
  wire [5:0] my_decoder_io_inst_type; // @[Id_stage.scala 294:32]
  wire [22:0] my_decoder_io_alu_op; // @[Id_stage.scala 294:32]
  wire  my_decoder_io_src1_sel; // @[Id_stage.scala 294:32]
  wire  my_decoder_io_src2_sel; // @[Id_stage.scala 294:32]
  wire  my_decoder_io_rf_we; // @[Id_stage.scala 294:32]
  wire  my_decoder_io_wb_sel; // @[Id_stage.scala 294:32]
  wire [8:0] my_decoder_io_br_type; // @[Id_stage.scala 294:32]
  wire  my_decoder_io_mem_en; // @[Id_stage.scala 294:32]
  wire  my_decoder_io_mem_wr; // @[Id_stage.scala 294:32]
  wire [6:0] my_decoder_io_mem_type; // @[Id_stage.scala 294:32]
  wire  my_decoder_io_rv64w; // @[Id_stage.scala 294:32]
  wire [2:0] my_decoder_io_ex_sel; // @[Id_stage.scala 294:32]
  wire [2:0] my_decoder_io_csr_op; // @[Id_stage.scala 294:32]
  wire [2:0] my_decoder_io_exc_type; // @[Id_stage.scala 294:32]
  wire  my_decoder_io_op_muldiv; // @[Id_stage.scala 294:32]
  wire  my_rf_clock; // @[Id_stage.scala 317:27]
  wire  my_rf_reset; // @[Id_stage.scala 317:27]
  wire [4:0] my_rf_io_raddr1; // @[Id_stage.scala 317:27]
  wire [4:0] my_rf_io_raddr2; // @[Id_stage.scala 317:27]
  wire [4:0] my_rf_io_waddr; // @[Id_stage.scala 317:27]
  wire [63:0] my_rf_io_wdata; // @[Id_stage.scala 317:27]
  wire  my_rf_io_wen; // @[Id_stage.scala 317:27]
  wire [63:0] my_rf_io_rdata1; // @[Id_stage.scala 317:27]
  wire [63:0] my_rf_io_rdata2; // @[Id_stage.scala 317:27]
  reg  ds_valid; // @[Id_stage.scala 284:30]
  reg [31:0] fs_ds_r_inst; // @[Id_stage.scala 285:30]
  reg [31:0] fs_ds_r_pc; // @[Id_stage.scala 285:30]
  wire  _T = io_if2id_ready & io_if2id_valid; // @[Decoupled.scala 52:35]
  wire [4:0] rf_raddr2 = fs_ds_r_inst[24:20]; // @[Id_stage.scala 299:23]
  wire [4:0] rs1 = fs_ds_r_inst[19:15]; // @[Id_stage.scala 300:23]
  wire [4:0] rd = fs_ds_r_inst[11:7]; // @[Id_stage.scala 301:23]
  wire [52:0] _imm_I_T_2 = fs_ds_r_inst[31] ? 53'h1fffffffffffff : 53'h0; // @[Bitwise.scala 77:12]
  wire [63:0] imm_I = {_imm_I_T_2,fs_ds_r_inst[30:20]}; // @[Cat.scala 33:92]
  wire [63:0] imm_S = {_imm_I_T_2,fs_ds_r_inst[30:25],rd}; // @[Cat.scala 33:92]
  wire [51:0] _imm_B_T_2 = fs_ds_r_inst[31] ? 52'hfffffffffffff : 52'h0; // @[Bitwise.scala 77:12]
  wire [63:0] imm_B = {_imm_B_T_2,fs_ds_r_inst[7],fs_ds_r_inst[30:25],fs_ds_r_inst[11:8],1'h0}; // @[Cat.scala 33:92]
  wire [32:0] _imm_U_T_2 = fs_ds_r_inst[31] ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 77:12]
  wire [63:0] imm_U = {_imm_U_T_2,fs_ds_r_inst[30:12],12'h0}; // @[Cat.scala 33:92]
  wire [43:0] _imm_J_T_2 = fs_ds_r_inst[31] ? 44'hfffffffffff : 44'h0; // @[Bitwise.scala 77:12]
  wire [63:0] imm_J = {_imm_J_T_2,fs_ds_r_inst[19:12],fs_ds_r_inst[20],fs_ds_r_inst[30:21],1'h0}; // @[Cat.scala 33:92]
  wire [63:0] _imm_T_7 = my_decoder_io_inst_type[1] ? imm_I : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _imm_T_8 = my_decoder_io_inst_type[2] ? imm_S : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _imm_T_9 = my_decoder_io_inst_type[3] ? imm_B : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _imm_T_10 = my_decoder_io_inst_type[4] ? imm_U : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _imm_T_11 = my_decoder_io_inst_type[5] ? imm_J : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _imm_T_13 = _imm_T_7 | _imm_T_8; // @[Mux.scala 27:73]
  wire [63:0] _imm_T_14 = _imm_T_13 | _imm_T_9; // @[Mux.scala 27:73]
  wire [63:0] _imm_T_15 = _imm_T_14 | _imm_T_10; // @[Mux.scala 27:73]
  wire [4:0] rf_raddr1 = my_decoder_io_inst_type[4] | my_decoder_io_inst_type[5] ? 5'h0 : rs1; // @[Id_stage.scala 318:31]
  wire  rs1_depend_es = io_es_forward_bits_en & io_es_forward_bits_dest == rf_raddr1; // @[Id_stage.scala 324:53]
  wire  rs1_depend_ms = io_ms_forward_bits_en & io_ms_forward_bits_dest == rf_raddr1; // @[Id_stage.scala 325:53]
  wire  rs1_depend_ws = io_ws_forward_bits_en & io_ws_forward_bits_dest == rf_raddr1; // @[Id_stage.scala 326:53]
  wire  _src1_block_T = ~io_es_forward_valid; // @[Id_stage.scala 328:50]
  wire  _src1_block_T_1 = rs1_depend_es & ~io_es_forward_valid; // @[Id_stage.scala 328:47]
  wire  _src1_block_T_2 = ~io_ms_forward_valid; // @[Id_stage.scala 329:50]
  wire  _src1_block_T_4 = _src1_block_T_1 | rs1_depend_ms & ~io_ms_forward_valid; // @[Id_stage.scala 329:29]
  wire  _src1_block_T_5 = ~io_ws_forward_valid; // @[Id_stage.scala 330:50]
  wire  src1_block = _src1_block_T_4 | rs1_depend_ws & ~io_ws_forward_valid; // @[Id_stage.scala 330:29]
  wire  rs2_depend_es = io_es_forward_bits_en & io_es_forward_bits_dest == rf_raddr2; // @[Id_stage.scala 333:53]
  wire  rs2_depend_ms = io_ms_forward_bits_en & io_ms_forward_bits_dest == rf_raddr2; // @[Id_stage.scala 334:53]
  wire  rs2_depend_ws = io_ws_forward_bits_en & io_ws_forward_bits_dest == rf_raddr2; // @[Id_stage.scala 335:53]
  wire  _src2_block_T_1 = rs2_depend_es & _src1_block_T; // @[Id_stage.scala 337:47]
  wire  _src2_block_T_4 = _src2_block_T_1 | rs2_depend_ms & _src1_block_T_2; // @[Id_stage.scala 338:29]
  wire  src2_block = _src2_block_T_4 | rs2_depend_ws & _src1_block_T_5; // @[Id_stage.scala 339:29]
  wire [63:0] _rf_rdata1_T = rs1_depend_ws ? io_ws_forward_bits_data : my_rf_io_rdata1; // @[Id_stage.scala 345:49]
  wire [63:0] _rf_rdata1_T_1 = rs1_depend_ms ? io_ms_forward_bits_data : _rf_rdata1_T; // @[Id_stage.scala 344:41]
  wire [63:0] _rf_rdata2_T = rs2_depend_ws ? io_ws_forward_bits_data : my_rf_io_rdata2; // @[Id_stage.scala 349:49]
  wire [63:0] _rf_rdata2_T_1 = rs2_depend_ms ? io_ms_forward_bits_data : _rf_rdata2_T; // @[Id_stage.scala 348:41]
  wire  ds_ready_go = ~src1_block & ~src2_block; // @[Id_stage.scala 384:39]
  ysyx_22051110_MyDecoder my_decoder ( // @[Id_stage.scala 294:32]
    .io_inst(my_decoder_io_inst),
    .io_inst_type(my_decoder_io_inst_type),
    .io_alu_op(my_decoder_io_alu_op),
    .io_src1_sel(my_decoder_io_src1_sel),
    .io_src2_sel(my_decoder_io_src2_sel),
    .io_rf_we(my_decoder_io_rf_we),
    .io_wb_sel(my_decoder_io_wb_sel),
    .io_br_type(my_decoder_io_br_type),
    .io_mem_en(my_decoder_io_mem_en),
    .io_mem_wr(my_decoder_io_mem_wr),
    .io_mem_type(my_decoder_io_mem_type),
    .io_rv64w(my_decoder_io_rv64w),
    .io_ex_sel(my_decoder_io_ex_sel),
    .io_csr_op(my_decoder_io_csr_op),
    .io_exc_type(my_decoder_io_exc_type),
    .io_op_muldiv(my_decoder_io_op_muldiv)
  );
  ysyx_22051110_RegFile my_rf ( // @[Id_stage.scala 317:27]
    .clock(my_rf_clock),
    .reset(my_rf_reset),
    .io_raddr1(my_rf_io_raddr1),
    .io_raddr2(my_rf_io_raddr2),
    .io_waddr(my_rf_io_waddr),
    .io_wdata(my_rf_io_wdata),
    .io_wen(my_rf_io_wen),
    .io_rdata1(my_rf_io_rdata1),
    .io_rdata2(my_rf_io_rdata2)
  );
  assign io_if2id_ready = ~ds_valid | ds_ready_go & io_id2ex_ready; // @[Id_stage.scala 385:37]
  assign io_id2ex_valid = ds_valid & ds_ready_go; // @[Id_stage.scala 386:37]
  assign io_id2ex_bits_alu_op = my_decoder_io_alu_op; // @[Id_stage.scala 356:33]
  assign io_id2ex_bits_src1_sel = my_decoder_io_src1_sel; // @[Id_stage.scala 357:33]
  assign io_id2ex_bits_src2_sel = my_decoder_io_src2_sel; // @[Id_stage.scala 358:33]
  assign io_id2ex_bits_br_type = my_decoder_io_br_type; // @[Id_stage.scala 360:33]
  assign io_id2ex_bits_gr_we = my_decoder_io_rf_we; // @[Id_stage.scala 361:33]
  assign io_id2ex_bits_wb_sel = my_decoder_io_wb_sel; // @[Id_stage.scala 362:33]
  assign io_id2ex_bits_mem_en = my_decoder_io_mem_en; // @[Id_stage.scala 363:33]
  assign io_id2ex_bits_mem_wr = my_decoder_io_mem_wr; // @[Id_stage.scala 364:33]
  assign io_id2ex_bits_mem_type = my_decoder_io_mem_type; // @[Id_stage.scala 365:33]
  assign io_id2ex_bits_rv64w = my_decoder_io_rv64w; // @[Id_stage.scala 366:33]
  assign io_id2ex_bits_ex_sel = my_decoder_io_ex_sel; // @[Id_stage.scala 367:33]
  assign io_id2ex_bits_csr_op = my_decoder_io_csr_op; // @[Id_stage.scala 368:33]
  assign io_id2ex_bits_exc_type = my_decoder_io_exc_type; // @[Id_stage.scala 369:33]
  assign io_id2ex_bits_op_muldiv = my_decoder_io_op_muldiv; // @[Id_stage.scala 371:33]
  assign io_id2ex_bits_is_fencei = fs_ds_r_inst[6:0] == 7'hf & fs_ds_r_inst[14:12] == 3'h1; // @[Id_stage.scala 292:56]
  assign io_id2ex_bits_dest = fs_ds_r_inst[11:7]; // @[Id_stage.scala 301:23]
  assign io_id2ex_bits_pc = fs_ds_r_pc; // @[Id_stage.scala 374:33]
  assign io_id2ex_bits_rs1 = rs1_depend_es ? io_es_forward_bits_data : _rf_rdata1_T_1; // @[Id_stage.scala 343:31]
  assign io_id2ex_bits_rs2 = rs2_depend_es ? io_es_forward_bits_data : _rf_rdata2_T_1; // @[Id_stage.scala 347:31]
  assign io_id2ex_bits_imm = _imm_T_15 | _imm_T_11; // @[Mux.scala 27:73]
  assign io_id2ex_bits_mem_wdata = rs2_depend_es ? io_es_forward_bits_data : _rf_rdata2_T_1; // @[Id_stage.scala 347:31]
  assign io_id2ex_bits_csr_num = fs_ds_r_inst[31:20]; // @[Id_stage.scala 381:40]
  assign my_decoder_io_inst = fs_ds_r_inst; // @[Id_stage.scala 295:28]
  assign my_rf_clock = clock;
  assign my_rf_reset = reset;
  assign my_rf_io_raddr1 = my_decoder_io_inst_type[4] | my_decoder_io_inst_type[5] ? 5'h0 : rs1; // @[Id_stage.scala 318:31]
  assign my_rf_io_raddr2 = fs_ds_r_inst[24:20]; // @[Id_stage.scala 299:23]
  assign my_rf_io_waddr = io_wb2rf_waddr; // @[Id_stage.scala 352:25]
  assign my_rf_io_wdata = io_wb2rf_wdata; // @[Id_stage.scala 353:25]
  assign my_rf_io_wen = io_wb2rf_rf_we; // @[Id_stage.scala 351:25]
  always @(posedge clock) begin
    if (reset) begin // @[Id_stage.scala 284:30]
      ds_valid <= 1'h0; // @[Id_stage.scala 284:30]
    end else if (io_exc_flush | io_br_flush) begin // @[Id_stage.scala 387:42]
      ds_valid <= 1'h0; // @[Id_stage.scala 388:24]
    end else if (io_if2id_ready) begin // @[Id_stage.scala 389:35]
      ds_valid <= io_if2id_valid; // @[Id_stage.scala 390:24]
    end
    if (reset) begin // @[Id_stage.scala 285:30]
      fs_ds_r_inst <= 32'h0; // @[Id_stage.scala 285:30]
    end else if (_T) begin // @[Id_stage.scala 286:25]
      fs_ds_r_inst <= io_if2id_bits_inst; // @[Id_stage.scala 287:20]
    end
    if (reset) begin // @[Id_stage.scala 285:30]
      fs_ds_r_pc <= 32'h0; // @[Id_stage.scala 285:30]
    end else if (_T) begin // @[Id_stage.scala 286:25]
      fs_ds_r_pc <= io_if2id_bits_pc; // @[Id_stage.scala 287:20]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ds_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  fs_ds_r_inst = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  fs_ds_r_pc = _RAND_2[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_MultBooth2(
  input         clock,
  input         reset,
  output        io_in_ready,
  input         io_in_valid,
  input         io_in_bits_flush,
  input         io_in_bits_mulw,
  input  [1:0]  io_in_bits_mul_signed,
  input  [63:0] io_in_bits_multiplicand,
  input  [63:0] io_in_bits_multiplier,
  output        io_out_valid,
  output [63:0] io_out_bits_result_hi,
  output [63:0] io_out_bits_result_lo
);
`ifdef RANDOMIZE_REG_INIT
  reg [159:0] _RAND_0;
  reg [95:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [159:0] _RAND_3;
  reg [63:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
  reg [131:0] src1_r; // @[MultUnit.scala 80:27]
  reg [66:0] src2_r; // @[MultUnit.scala 81:27]
  reg  mulw_r; // @[MultUnit.scala 83:27]
  reg [131:0] res_r; // @[MultUnit.scala 84:27]
  reg [32:0] cnt; // @[MultUnit.scala 85:27]
  reg  done; // @[MultUnit.scala 86:27]
  wire  last_step = cnt[32] & ~mulw_r | cnt[16] & mulw_r; // @[MultUnit.scala 88:57]
  wire  working = |cnt; // @[MultUnit.scala 89:25]
  wire  _T_1 = io_in_ready & io_in_valid; // @[Decoupled.scala 52:35]
  wire [32:0] _cnt_T_1 = {cnt[31:0],1'h0}; // @[Cat.scala 33:92]
  wire [132:0] src1_double = {src1_r,1'h0}; // @[Cat.scala 33:92]
  wire [131:0] _src1_neg_T = ~src1_r; // @[MultUnit.scala 100:27]
  wire [131:0] src1_neg = _src1_neg_T + 132'h1; // @[MultUnit.scala 100:35]
  wire [132:0] src1_double_neg = {src1_neg,1'h0}; // @[Cat.scala 33:92]
  wire [67:0] _src1_r_T_3 = io_in_bits_multiplicand[63] ? 68'hfffffffffffffffff : 68'h0; // @[Bitwise.scala 77:12]
  wire [67:0] _src1_r_T_4 = io_in_bits_mul_signed[1] ? _src1_r_T_3 : 68'h0; // @[MultUnit.scala 103:28]
  wire [131:0] _src1_r_T_5 = {_src1_r_T_4,io_in_bits_multiplicand}; // @[Cat.scala 33:92]
  wire [1:0] _src2_r_T_3 = io_in_bits_multiplier[63] ? 2'h3 : 2'h0; // @[Bitwise.scala 77:12]
  wire [1:0] _src2_r_T_4 = io_in_bits_mul_signed[0] ? _src2_r_T_3 : 2'h0; // @[MultUnit.scala 105:28]
  wire [66:0] _src2_r_T_5 = {_src2_r_T_4,io_in_bits_multiplier,1'h0}; // @[Cat.scala 33:92]
  wire [131:0] _GEN_6 = _T_1 ? 132'h0 : res_r; // @[MultUnit.scala 102:21 109:18 84:27]
  wire [1:0] _sel_T_2 = 3'h1 == src2_r[2:0] ? 2'h2 : 2'h1; // @[Mux.scala 81:58]
  wire [1:0] _sel_T_4 = 3'h2 == src2_r[2:0] ? 2'h2 : _sel_T_2; // @[Mux.scala 81:58]
  wire [2:0] _sel_T_6 = 3'h3 == src2_r[2:0] ? 3'h4 : {{1'd0}, _sel_T_4}; // @[Mux.scala 81:58]
  wire [3:0] _sel_T_8 = 3'h4 == src2_r[2:0] ? 4'h8 : {{1'd0}, _sel_T_6}; // @[Mux.scala 81:58]
  wire [4:0] _sel_T_10 = 3'h5 == src2_r[2:0] ? 5'h10 : {{1'd0}, _sel_T_8}; // @[Mux.scala 81:58]
  wire [4:0] _sel_T_12 = 3'h6 == src2_r[2:0] ? 5'h10 : _sel_T_10; // @[Mux.scala 81:58]
  wire [4:0] sel = 3'h7 == src2_r[2:0] ? 5'h1 : _sel_T_12; // @[Mux.scala 81:58]
  wire [131:0] _p_T_6 = sel[1] ? src1_r : 132'h0; // @[Mux.scala 27:73]
  wire [132:0] _p_T_7 = sel[2] ? src1_double : 133'h0; // @[Mux.scala 27:73]
  wire [132:0] _p_T_8 = sel[3] ? src1_double_neg : 133'h0; // @[Mux.scala 27:73]
  wire [131:0] _p_T_9 = sel[4] ? src1_neg : 132'h0; // @[Mux.scala 27:73]
  wire [132:0] _GEN_12 = {{1'd0}, _p_T_6}; // @[Mux.scala 27:73]
  wire [132:0] _p_T_11 = _GEN_12 | _p_T_7; // @[Mux.scala 27:73]
  wire [132:0] _p_T_12 = _p_T_11 | _p_T_8; // @[Mux.scala 27:73]
  wire [132:0] _GEN_13 = {{1'd0}, _p_T_9}; // @[Mux.scala 27:73]
  wire [132:0] p = _p_T_12 | _GEN_13; // @[Mux.scala 27:73]
  wire [132:0] _GEN_14 = {{1'd0}, res_r}; // @[MultUnit.scala 131:21]
  wire [132:0] _res_r_T_1 = p + _GEN_14; // @[MultUnit.scala 131:21]
  wire [131:0] _src1_r_T_7 = {src1_r[129:0],2'h0}; // @[Cat.scala 33:92]
  wire [1:0] _src2_r_T_8 = src2_r[66] ? 2'h3 : 2'h0; // @[Bitwise.scala 77:12]
  wire [66:0] _src2_r_T_10 = {_src2_r_T_8,src2_r[66:2]}; // @[Cat.scala 33:92]
  wire [132:0] _GEN_7 = working ? _res_r_T_1 : {{1'd0}, _GEN_6}; // @[MultUnit.scala 130:19 131:16]
  wire  _GEN_10 = last_step | done; // @[MultUnit.scala 138:27 139:14 86:27]
  wire [63:0] _io_out_bits_result_hi_T_2 = res_r[31] ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 77:12]
  wire [31:0] _io_out_bits_result_lo_T_2 = res_r[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [31:0] _io_out_bits_result_lo_T_4 = mulw_r ? _io_out_bits_result_lo_T_2 : res_r[63:32]; // @[MultUnit.scala 145:37]
  wire [132:0] _GEN_15 = reset ? 133'h0 : _GEN_7; // @[MultUnit.scala 84:{27,27}]
  assign io_in_ready = ~working; // @[MultUnit.scala 142:21]
  assign io_out_valid = done; // @[MultUnit.scala 143:18]
  assign io_out_bits_result_hi = mulw_r ? _io_out_bits_result_hi_T_2 : res_r[127:64]; // @[MultUnit.scala 144:33]
  assign io_out_bits_result_lo = {_io_out_bits_result_lo_T_4,res_r[31:0]}; // @[Cat.scala 33:92]
  always @(posedge clock) begin
    if (reset) begin // @[MultUnit.scala 80:27]
      src1_r <= 132'h0; // @[MultUnit.scala 80:27]
    end else if (working) begin // @[MultUnit.scala 130:19]
      src1_r <= _src1_r_T_7; // @[MultUnit.scala 132:16]
    end else if (_T_1) begin // @[MultUnit.scala 102:21]
      src1_r <= _src1_r_T_5; // @[MultUnit.scala 103:18]
    end
    if (reset) begin // @[MultUnit.scala 81:27]
      src2_r <= 67'h0; // @[MultUnit.scala 81:27]
    end else if (working) begin // @[MultUnit.scala 130:19]
      src2_r <= _src2_r_T_10; // @[MultUnit.scala 133:16]
    end else if (_T_1) begin // @[MultUnit.scala 102:21]
      src2_r <= _src2_r_T_5; // @[MultUnit.scala 105:18]
    end
    if (reset) begin // @[MultUnit.scala 83:27]
      mulw_r <= 1'h0; // @[MultUnit.scala 83:27]
    end else if (_T_1) begin // @[MultUnit.scala 102:21]
      mulw_r <= io_in_bits_mulw; // @[MultUnit.scala 107:18]
    end
    res_r <= _GEN_15[131:0]; // @[MultUnit.scala 84:{27,27}]
    if (reset) begin // @[MultUnit.scala 85:27]
      cnt <= 33'h0; // @[MultUnit.scala 85:27]
    end else if (io_in_bits_flush | last_step) begin // @[MultUnit.scala 90:40]
      cnt <= 33'h0; // @[MultUnit.scala 91:13]
    end else if (_T_1) begin // @[MultUnit.scala 92:27]
      cnt <= 33'h1; // @[MultUnit.scala 93:13]
    end else begin
      cnt <= _cnt_T_1; // @[MultUnit.scala 95:13]
    end
    if (reset) begin // @[MultUnit.scala 86:27]
      done <= 1'h0; // @[MultUnit.scala 86:27]
    end else if (done) begin // @[MultUnit.scala 136:16]
      done <= 1'h0; // @[MultUnit.scala 137:14]
    end else begin
      done <= _GEN_10;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {5{`RANDOM}};
  src1_r = _RAND_0[131:0];
  _RAND_1 = {3{`RANDOM}};
  src2_r = _RAND_1[66:0];
  _RAND_2 = {1{`RANDOM}};
  mulw_r = _RAND_2[0:0];
  _RAND_3 = {5{`RANDOM}};
  res_r = _RAND_3[131:0];
  _RAND_4 = {2{`RANDOM}};
  cnt = _RAND_4[32:0];
  _RAND_5 = {1{`RANDOM}};
  done = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_MultUnit(
  input         clock,
  input         reset,
  output        io_in_ready,
  input         io_in_valid,
  input         io_in_bits_flush,
  input         io_in_bits_mulw,
  input  [1:0]  io_in_bits_mul_signed,
  input  [63:0] io_in_bits_multiplicand,
  input  [63:0] io_in_bits_multiplier,
  output        io_out_valid,
  output [63:0] io_out_bits_result_hi,
  output [63:0] io_out_bits_result_lo
);
  wire  mult_core_clock; // @[MultUnit.scala 10:27]
  wire  mult_core_reset; // @[MultUnit.scala 10:27]
  wire  mult_core_io_in_ready; // @[MultUnit.scala 10:27]
  wire  mult_core_io_in_valid; // @[MultUnit.scala 10:27]
  wire  mult_core_io_in_bits_flush; // @[MultUnit.scala 10:27]
  wire  mult_core_io_in_bits_mulw; // @[MultUnit.scala 10:27]
  wire [1:0] mult_core_io_in_bits_mul_signed; // @[MultUnit.scala 10:27]
  wire [63:0] mult_core_io_in_bits_multiplicand; // @[MultUnit.scala 10:27]
  wire [63:0] mult_core_io_in_bits_multiplier; // @[MultUnit.scala 10:27]
  wire  mult_core_io_out_valid; // @[MultUnit.scala 10:27]
  wire [63:0] mult_core_io_out_bits_result_hi; // @[MultUnit.scala 10:27]
  wire [63:0] mult_core_io_out_bits_result_lo; // @[MultUnit.scala 10:27]
  ysyx_22051110_MultBooth2 mult_core ( // @[MultUnit.scala 10:27]
    .clock(mult_core_clock),
    .reset(mult_core_reset),
    .io_in_ready(mult_core_io_in_ready),
    .io_in_valid(mult_core_io_in_valid),
    .io_in_bits_flush(mult_core_io_in_bits_flush),
    .io_in_bits_mulw(mult_core_io_in_bits_mulw),
    .io_in_bits_mul_signed(mult_core_io_in_bits_mul_signed),
    .io_in_bits_multiplicand(mult_core_io_in_bits_multiplicand),
    .io_in_bits_multiplier(mult_core_io_in_bits_multiplier),
    .io_out_valid(mult_core_io_out_valid),
    .io_out_bits_result_hi(mult_core_io_out_bits_result_hi),
    .io_out_bits_result_lo(mult_core_io_out_bits_result_lo)
  );
  assign io_in_ready = mult_core_io_in_ready; // @[MultUnit.scala 11:8]
  assign io_out_valid = mult_core_io_out_valid; // @[MultUnit.scala 11:8]
  assign io_out_bits_result_hi = mult_core_io_out_bits_result_hi; // @[MultUnit.scala 11:8]
  assign io_out_bits_result_lo = mult_core_io_out_bits_result_lo; // @[MultUnit.scala 11:8]
  assign mult_core_clock = clock;
  assign mult_core_reset = reset;
  assign mult_core_io_in_valid = io_in_valid; // @[MultUnit.scala 11:8]
  assign mult_core_io_in_bits_flush = io_in_bits_flush; // @[MultUnit.scala 11:8]
  assign mult_core_io_in_bits_mulw = io_in_bits_mulw; // @[MultUnit.scala 11:8]
  assign mult_core_io_in_bits_mul_signed = io_in_bits_mul_signed; // @[MultUnit.scala 11:8]
  assign mult_core_io_in_bits_multiplicand = io_in_bits_multiplicand; // @[MultUnit.scala 11:8]
  assign mult_core_io_in_bits_multiplier = io_in_bits_multiplier; // @[MultUnit.scala 11:8]
endmodule
module ysyx_22051110_DivRestoreRem(
  input         clock,
  input         reset,
  output        io_in_ready,
  input         io_in_valid,
  input         io_in_bits_flush,
  input         io_in_bits_divw,
  input         io_in_bits_div_signed,
  input  [63:0] io_in_bits_dividend,
  input  [63:0] io_in_bits_divisor,
  output        io_out_valid,
  output [63:0] io_out_bits_quotient,
  output [63:0] io_out_bits_reminder
);
`ifdef RANDOMIZE_REG_INIT
  reg [127:0] _RAND_0;
  reg [63:0] _RAND_1;
  reg [63:0] _RAND_2;
  reg [63:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [63:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  reg [127:0] dividend_r; // @[DivUnit.scala 19:29]
  reg [63:0] divisor_r; // @[DivUnit.scala 20:29]
  reg [63:0] quotient_r; // @[DivUnit.scala 21:29]
  reg [63:0] reminder_r; // @[DivUnit.scala 22:29]
  reg  divw_r; // @[DivUnit.scala 23:29]
  reg  sel_q_sign; // @[DivUnit.scala 25:29]
  reg  sel_r_sign; // @[DivUnit.scala 26:29]
  reg  done; // @[DivUnit.scala 27:29]
  reg [63:0] cnt; // @[DivUnit.scala 28:29]
  wire  dividend_msb = io_in_bits_divw ? io_in_bits_dividend[31] : io_in_bits_dividend[63]; // @[DivUnit.scala 29:27]
  wire  divisor_msb = io_in_bits_divw ? io_in_bits_divisor[31] : io_in_bits_divisor[63]; // @[DivUnit.scala 30:27]
  wire  _dividend_lo_T = io_in_bits_div_signed & dividend_msb; // @[DivUnit.scala 31:50]
  wire [63:0] _dividend_lo_T_1 = ~io_in_bits_dividend; // @[DivUnit.scala 31:67]
  wire [63:0] _dividend_lo_T_3 = _dividend_lo_T_1 + 64'h1; // @[DivUnit.scala 31:88]
  wire [63:0] dividend_lo = io_in_bits_div_signed & dividend_msb ? _dividend_lo_T_3 : io_in_bits_dividend; // @[DivUnit.scala 31:27]
  wire  last_step = cnt[63] & ~divw_r | cnt[31] & divw_r; // @[DivUnit.scala 34:55]
  wire  working = |cnt; // @[DivUnit.scala 35:29]
  wire  _T_1 = io_in_ready & io_in_valid; // @[Decoupled.scala 52:35]
  wire [63:0] _cnt_T_1 = {cnt[62:0],1'h0}; // @[Cat.scala 33:92]
  wire [31:0] _dividend_r_T_1 = io_in_bits_divw ? 32'h0 : dividend_lo[63:32]; // @[DivUnit.scala 46:44]
  wire [127:0] _dividend_r_T_3 = {64'h0,_dividend_r_T_1,dividend_lo[31:0]}; // @[Cat.scala 33:92]
  wire [63:0] _divisor_r_T_1 = ~io_in_bits_divisor; // @[DivUnit.scala 47:69]
  wire [63:0] _divisor_r_T_3 = _divisor_r_T_1 + 64'h1; // @[DivUnit.scala 47:90]
  wire [64:0] _add_src1_T_1 = {32'h0,dividend_r[63:31]}; // @[Cat.scala 33:92]
  wire [64:0] add_src1 = divw_r ? _add_src1_T_1 : dividend_r[127:63]; // @[DivUnit.scala 58:28]
  wire [63:0] _add_src2_T_1 = {32'h0,divisor_r[31:0]}; // @[Cat.scala 33:92]
  wire [63:0] _add_src2_T_2 = divw_r ? _add_src2_T_1 : divisor_r; // @[DivUnit.scala 59:43]
  wire [64:0] _add_src2_T_3 = {1'h0,_add_src2_T_2}; // @[Cat.scala 33:92]
  wire [64:0] _add_src2_T_4 = ~_add_src2_T_3; // @[DivUnit.scala 59:25]
  wire [64:0] add_src2 = _add_src2_T_4 + 65'h1; // @[DivUnit.scala 59:104]
  wire [64:0] add_res = add_src1 + add_src2; // @[DivUnit.scala 60:34]
  wire [63:0] _next_valw_T_3 = {dividend_r[62:0],1'h0}; // @[Cat.scala 33:92]
  wire [63:0] _next_valw_T_6 = {add_res[31:0],dividend_r[30:0],1'h0}; // @[Cat.scala 33:92]
  wire [63:0] _next_valw_T_7 = add_res[64] ? _next_valw_T_3 : _next_valw_T_6; // @[DivUnit.scala 61:56]
  wire [127:0] next_valw = {dividend_r[127:64],_next_valw_T_7}; // @[Cat.scala 33:92]
  wire [127:0] _next_val_T_2 = {dividend_r[126:0],1'h0}; // @[Cat.scala 33:92]
  wire [127:0] _next_val_T_5 = {add_res[63:0],dividend_r[62:0],1'h0}; // @[Cat.scala 33:92]
  wire  _quotient_r_T_2 = ~add_res[64]; // @[DivUnit.scala 67:53]
  wire [63:0] _quotient_r_T_3 = {quotient_r[62:0],_quotient_r_T_2}; // @[Cat.scala 33:92]
  wire [63:0] _rvs_quotient_r_T = ~quotient_r; // @[DivUnit.scala 70:30]
  wire [63:0] rvs_quotient_r = _rvs_quotient_r_T + 64'h1; // @[DivUnit.scala 70:42]
  wire [63:0] _rvs_reminder_r_T = ~reminder_r; // @[DivUnit.scala 71:30]
  wire [63:0] rvs_reminder_r = _rvs_reminder_r_T + 64'h1; // @[DivUnit.scala 71:42]
  wire  _GEN_13 = last_step | done; // @[DivUnit.scala 75:31 76:18 27:29]
  assign io_in_ready = ~working; // @[DivUnit.scala 79:21]
  assign io_out_valid = done; // @[DivUnit.scala 80:18]
  assign io_out_bits_quotient = sel_q_sign ? rvs_quotient_r : quotient_r; // @[DivUnit.scala 81:32]
  assign io_out_bits_reminder = sel_r_sign ? rvs_reminder_r : reminder_r; // @[DivUnit.scala 82:32]
  always @(posedge clock) begin
    if (reset) begin // @[DivUnit.scala 19:29]
      dividend_r <= 128'h0; // @[DivUnit.scala 19:29]
    end else if (working) begin // @[DivUnit.scala 65:22]
      if (divw_r) begin // @[DivUnit.scala 66:30]
        dividend_r <= next_valw;
      end else if (add_res[64]) begin // @[DivUnit.scala 63:28]
        dividend_r <= _next_val_T_2;
      end else begin
        dividend_r <= _next_val_T_5;
      end
    end else if (_T_1) begin // @[DivUnit.scala 45:25]
      dividend_r <= _dividend_r_T_3; // @[DivUnit.scala 46:24]
    end
    if (reset) begin // @[DivUnit.scala 20:29]
      divisor_r <= 64'h0; // @[DivUnit.scala 20:29]
    end else if (_T_1) begin // @[DivUnit.scala 45:25]
      if (io_in_bits_div_signed & divisor_msb) begin // @[DivUnit.scala 47:30]
        divisor_r <= _divisor_r_T_3;
      end else begin
        divisor_r <= io_in_bits_divisor;
      end
    end
    if (reset) begin // @[DivUnit.scala 21:29]
      quotient_r <= 64'h0; // @[DivUnit.scala 21:29]
    end else if (working) begin // @[DivUnit.scala 65:22]
      quotient_r <= _quotient_r_T_3; // @[DivUnit.scala 67:24]
    end else if (_T_1) begin // @[DivUnit.scala 45:25]
      quotient_r <= 64'h0; // @[DivUnit.scala 48:24]
    end
    if (reset) begin // @[DivUnit.scala 22:29]
      reminder_r <= 64'h0; // @[DivUnit.scala 22:29]
    end else if (working) begin // @[DivUnit.scala 65:22]
      if (add_res[64]) begin // @[DivUnit.scala 68:30]
        reminder_r <= add_src1[63:0];
      end else begin
        reminder_r <= add_res[63:0];
      end
    end else if (_T_1) begin // @[DivUnit.scala 45:25]
      reminder_r <= 64'h0; // @[DivUnit.scala 49:24]
    end
    if (reset) begin // @[DivUnit.scala 23:29]
      divw_r <= 1'h0; // @[DivUnit.scala 23:29]
    end else if (_T_1) begin // @[DivUnit.scala 45:25]
      divw_r <= io_in_bits_divw; // @[DivUnit.scala 50:24]
    end
    if (reset) begin // @[DivUnit.scala 25:29]
      sel_q_sign <= 1'h0; // @[DivUnit.scala 25:29]
    end else if (_T_1) begin // @[DivUnit.scala 45:25]
      sel_q_sign <= io_in_bits_div_signed & (dividend_msb ^ divisor_msb); // @[DivUnit.scala 52:24]
    end
    if (reset) begin // @[DivUnit.scala 26:29]
      sel_r_sign <= 1'h0; // @[DivUnit.scala 26:29]
    end else if (_T_1) begin // @[DivUnit.scala 45:25]
      sel_r_sign <= _dividend_lo_T; // @[DivUnit.scala 53:24]
    end
    if (reset) begin // @[DivUnit.scala 27:29]
      done <= 1'h0; // @[DivUnit.scala 27:29]
    end else if (done) begin // @[DivUnit.scala 73:20]
      done <= 1'h0; // @[DivUnit.scala 74:18]
    end else begin
      done <= _GEN_13;
    end
    if (reset) begin // @[DivUnit.scala 28:29]
      cnt <= 64'h0; // @[DivUnit.scala 28:29]
    end else if (io_in_bits_flush | last_step) begin // @[DivUnit.scala 36:44]
      cnt <= 64'h0; // @[DivUnit.scala 37:17]
    end else if (_T_1) begin // @[DivUnit.scala 38:31]
      cnt <= 64'h1; // @[DivUnit.scala 39:17]
    end else begin
      cnt <= _cnt_T_1; // @[DivUnit.scala 41:17]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {4{`RANDOM}};
  dividend_r = _RAND_0[127:0];
  _RAND_1 = {2{`RANDOM}};
  divisor_r = _RAND_1[63:0];
  _RAND_2 = {2{`RANDOM}};
  quotient_r = _RAND_2[63:0];
  _RAND_3 = {2{`RANDOM}};
  reminder_r = _RAND_3[63:0];
  _RAND_4 = {1{`RANDOM}};
  divw_r = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  sel_q_sign = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  sel_r_sign = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  done = _RAND_7[0:0];
  _RAND_8 = {2{`RANDOM}};
  cnt = _RAND_8[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_DivUnit(
  input         clock,
  input         reset,
  output        io_in_ready,
  input         io_in_valid,
  input         io_in_bits_flush,
  input         io_in_bits_divw,
  input         io_in_bits_div_signed,
  input  [63:0] io_in_bits_dividend,
  input  [63:0] io_in_bits_divisor,
  output        io_out_valid,
  output [63:0] io_out_bits_quotient,
  output [63:0] io_out_bits_reminder
);
  wire  div_core_clock; // @[DivUnit.scala 10:26]
  wire  div_core_reset; // @[DivUnit.scala 10:26]
  wire  div_core_io_in_ready; // @[DivUnit.scala 10:26]
  wire  div_core_io_in_valid; // @[DivUnit.scala 10:26]
  wire  div_core_io_in_bits_flush; // @[DivUnit.scala 10:26]
  wire  div_core_io_in_bits_divw; // @[DivUnit.scala 10:26]
  wire  div_core_io_in_bits_div_signed; // @[DivUnit.scala 10:26]
  wire [63:0] div_core_io_in_bits_dividend; // @[DivUnit.scala 10:26]
  wire [63:0] div_core_io_in_bits_divisor; // @[DivUnit.scala 10:26]
  wire  div_core_io_out_valid; // @[DivUnit.scala 10:26]
  wire [63:0] div_core_io_out_bits_quotient; // @[DivUnit.scala 10:26]
  wire [63:0] div_core_io_out_bits_reminder; // @[DivUnit.scala 10:26]
  ysyx_22051110_DivRestoreRem div_core ( // @[DivUnit.scala 10:26]
    .clock(div_core_clock),
    .reset(div_core_reset),
    .io_in_ready(div_core_io_in_ready),
    .io_in_valid(div_core_io_in_valid),
    .io_in_bits_flush(div_core_io_in_bits_flush),
    .io_in_bits_divw(div_core_io_in_bits_divw),
    .io_in_bits_div_signed(div_core_io_in_bits_div_signed),
    .io_in_bits_dividend(div_core_io_in_bits_dividend),
    .io_in_bits_divisor(div_core_io_in_bits_divisor),
    .io_out_valid(div_core_io_out_valid),
    .io_out_bits_quotient(div_core_io_out_bits_quotient),
    .io_out_bits_reminder(div_core_io_out_bits_reminder)
  );
  assign io_in_ready = div_core_io_in_ready; // @[DivUnit.scala 11:8]
  assign io_out_valid = div_core_io_out_valid; // @[DivUnit.scala 11:8]
  assign io_out_bits_quotient = div_core_io_out_bits_quotient; // @[DivUnit.scala 11:8]
  assign io_out_bits_reminder = div_core_io_out_bits_reminder; // @[DivUnit.scala 11:8]
  assign div_core_clock = clock;
  assign div_core_reset = reset;
  assign div_core_io_in_valid = io_in_valid; // @[DivUnit.scala 11:8]
  assign div_core_io_in_bits_flush = io_in_bits_flush; // @[DivUnit.scala 11:8]
  assign div_core_io_in_bits_divw = io_in_bits_divw; // @[DivUnit.scala 11:8]
  assign div_core_io_in_bits_div_signed = io_in_bits_div_signed; // @[DivUnit.scala 11:8]
  assign div_core_io_in_bits_dividend = io_in_bits_dividend; // @[DivUnit.scala 11:8]
  assign div_core_io_in_bits_divisor = io_in_bits_divisor; // @[DivUnit.scala 11:8]
endmodule
module ysyx_22051110_Alu(
  input         clock,
  input         reset,
  output        io_in_ready,
  input         io_in_valid,
  input  [63:0] io_in_bits_src1,
  input  [63:0] io_in_bits_src2,
  input  [22:0] io_in_bits_alu_op,
  input         io_in_bits_alu_flush,
  output        io_out_valid,
  output [63:0] io_out_bits_res,
  output        io_out_bits_cout,
  output        io_out_bits_overflow
);
  wire  my_mul_clock; // @[Alu.scala 65:24]
  wire  my_mul_reset; // @[Alu.scala 65:24]
  wire  my_mul_io_in_ready; // @[Alu.scala 65:24]
  wire  my_mul_io_in_valid; // @[Alu.scala 65:24]
  wire  my_mul_io_in_bits_flush; // @[Alu.scala 65:24]
  wire  my_mul_io_in_bits_mulw; // @[Alu.scala 65:24]
  wire [1:0] my_mul_io_in_bits_mul_signed; // @[Alu.scala 65:24]
  wire [63:0] my_mul_io_in_bits_multiplicand; // @[Alu.scala 65:24]
  wire [63:0] my_mul_io_in_bits_multiplier; // @[Alu.scala 65:24]
  wire  my_mul_io_out_valid; // @[Alu.scala 65:24]
  wire [63:0] my_mul_io_out_bits_result_hi; // @[Alu.scala 65:24]
  wire [63:0] my_mul_io_out_bits_result_lo; // @[Alu.scala 65:24]
  wire  my_div_clock; // @[Alu.scala 88:24]
  wire  my_div_reset; // @[Alu.scala 88:24]
  wire  my_div_io_in_ready; // @[Alu.scala 88:24]
  wire  my_div_io_in_valid; // @[Alu.scala 88:24]
  wire  my_div_io_in_bits_flush; // @[Alu.scala 88:24]
  wire  my_div_io_in_bits_divw; // @[Alu.scala 88:24]
  wire  my_div_io_in_bits_div_signed; // @[Alu.scala 88:24]
  wire [63:0] my_div_io_in_bits_dividend; // @[Alu.scala 88:24]
  wire [63:0] my_div_io_in_bits_divisor; // @[Alu.scala 88:24]
  wire  my_div_io_out_valid; // @[Alu.scala 88:24]
  wire [63:0] my_div_io_out_bits_quotient; // @[Alu.scala 88:24]
  wire [63:0] my_div_io_out_bits_reminder; // @[Alu.scala 88:24]
  wire  is_mul = |io_in_bits_alu_op[14:10]; // @[Alu.scala 34:45]
  wire  is_div = |io_in_bits_alu_op[22:15]; // @[Alu.scala 35:45]
  wire [63:0] cin = io_in_bits_alu_op[1] ? 64'h1 : 64'h0; // @[Alu.scala 37:23]
  wire [63:0] _add_src2_T_2 = ~io_in_bits_src2; // @[Alu.scala 39:54]
  wire [63:0] add_src2 = io_in_bits_alu_op[1] ? _add_src2_T_2 : io_in_bits_src2; // @[Alu.scala 39:23]
  wire [64:0] _add_res_T = io_in_bits_src1 + add_src2; // @[Alu.scala 40:30]
  wire [64:0] _GEN_0 = {{1'd0}, cin}; // @[Alu.scala 40:43]
  wire [64:0] add_res = _add_res_T + _GEN_0; // @[Alu.scala 40:43]
  wire [63:0] and_res = io_in_bits_src1 & io_in_bits_src2; // @[Alu.scala 42:36]
  wire [63:0] or_res = io_in_bits_src1 | io_in_bits_src2; // @[Alu.scala 43:36]
  wire [63:0] xor_res = io_in_bits_src1 ^ io_in_bits_src2; // @[Alu.scala 44:36]
  wire [5:0] shift_len = io_in_bits_src2[5:0]; // @[Alu.scala 46:38]
  wire [4:0] shift_len_w = io_in_bits_src2[4:0]; // @[Alu.scala 47:38]
  wire [126:0] _GEN_3 = {{63'd0}, io_in_bits_src1}; // @[Alu.scala 48:39]
  wire [126:0] sll = _GEN_3 << shift_len; // @[Alu.scala 48:39]
  wire [63:0] srl = io_in_bits_src1 >> shift_len; // @[Alu.scala 49:39]
  wire [31:0] srlw = io_in_bits_src1[31:0] >> shift_len_w; // @[Alu.scala 51:48]
  wire [31:0] _sraw_T_1 = io_in_bits_src1[31:0]; // @[Alu.scala 52:49]
  wire  _io_out_bits_overflow_T_4 = io_in_bits_src1[63] ^ io_in_bits_src2[63]; // @[Alu.scala 56:34]
  wire  _io_out_bits_overflow_T_8 = io_in_bits_src1[63] ^ add_res[63]; // @[Alu.scala 56:82]
  wire  _io_out_bits_overflow_T_9 = ~(io_in_bits_src1[63] ^ io_in_bits_src2[63]) & (io_in_bits_src1[63] ^ add_res[63]); // @[Alu.scala 56:58]
  wire  _io_out_bits_overflow_T_16 = _io_out_bits_overflow_T_4 & _io_out_bits_overflow_T_8; // @[Alu.scala 57:58]
  wire [1:0] _my_mul_io_in_bits_mul_signed_T_4 = io_in_bits_alu_op[12] ? 2'h0 : 2'h3; // @[Alu.scala 70:44]
  wire [127:0] mul_res_s = {my_mul_io_out_bits_result_hi,my_mul_io_out_bits_result_lo}; // @[Cat.scala 33:92]
  wire  _my_div_io_in_bits_divw_T_4 = io_in_bits_alu_op[17] | io_in_bits_alu_op[18] | io_in_bits_alu_op[21]; // @[Alu.scala 91:83]
  wire  _my_div_io_in_bits_div_signed_T_4 = io_in_bits_alu_op[15] | io_in_bits_alu_op[17] | io_in_bits_alu_op[19]; // @[Alu.scala 93:83]
  wire [31:0] divw_res = my_div_io_out_bits_quotient[31:0]; // @[Alu.scala 99:48]
  wire [31:0] remw_res = my_div_io_out_bits_reminder[31:0]; // @[Alu.scala 103:48]
  wire [63:0] _io_out_bits_res_T_11 = $signed(io_in_bits_src1) >>> shift_len; // @[Alu.scala 114:51]
  wire [31:0] _io_out_bits_res_T_14 = $signed(_sraw_T_1) >>> shift_len_w; // @[Alu.scala 116:52]
  wire [31:0] _io_out_bits_res_T_29 = divw_res[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [63:0] _io_out_bits_res_T_31 = {_io_out_bits_res_T_29,divw_res}; // @[Cat.scala 33:92]
  wire [31:0] _io_out_bits_res_T_43 = remw_res[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [63:0] _io_out_bits_res_T_45 = {_io_out_bits_res_T_43,remw_res}; // @[Cat.scala 33:92]
  wire [63:0] _io_out_bits_res_T_52 = io_in_bits_alu_op[0] ? add_res[63:0] : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_53 = io_in_bits_alu_op[1] ? add_res[63:0] : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_54 = io_in_bits_alu_op[2] ? and_res : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_55 = io_in_bits_alu_op[3] ? or_res : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_56 = io_in_bits_alu_op[4] ? xor_res : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_57 = io_in_bits_alu_op[5] ? sll[63:0] : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_58 = io_in_bits_alu_op[6] ? srl : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_59 = io_in_bits_alu_op[7] ? _io_out_bits_res_T_11 : 64'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_out_bits_res_T_60 = io_in_bits_alu_op[8] ? srlw : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_out_bits_res_T_61 = io_in_bits_alu_op[9] ? _io_out_bits_res_T_14 : 32'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_62 = io_in_bits_alu_op[10] ? mul_res_s[63:0] : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_63 = io_in_bits_alu_op[11] ? mul_res_s[127:64] : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_64 = io_in_bits_alu_op[12] ? mul_res_s[127:64] : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_65 = io_in_bits_alu_op[13] ? mul_res_s[63:0] : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_66 = io_in_bits_alu_op[14] ? my_mul_io_out_bits_result_lo : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_67 = io_in_bits_alu_op[15] ? my_div_io_out_bits_quotient : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_68 = io_in_bits_alu_op[16] ? my_div_io_out_bits_quotient : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_69 = io_in_bits_alu_op[17] ? _io_out_bits_res_T_31 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_70 = io_in_bits_alu_op[18] ? _io_out_bits_res_T_31 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_71 = io_in_bits_alu_op[19] ? my_div_io_out_bits_reminder : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_72 = io_in_bits_alu_op[20] ? my_div_io_out_bits_reminder : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_73 = io_in_bits_alu_op[21] ? _io_out_bits_res_T_45 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_74 = io_in_bits_alu_op[22] ? _io_out_bits_res_T_45 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_75 = _io_out_bits_res_T_52 | _io_out_bits_res_T_53; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_76 = _io_out_bits_res_T_75 | _io_out_bits_res_T_54; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_77 = _io_out_bits_res_T_76 | _io_out_bits_res_T_55; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_78 = _io_out_bits_res_T_77 | _io_out_bits_res_T_56; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_79 = _io_out_bits_res_T_78 | _io_out_bits_res_T_57; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_80 = _io_out_bits_res_T_79 | _io_out_bits_res_T_58; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_81 = _io_out_bits_res_T_80 | _io_out_bits_res_T_59; // @[Mux.scala 27:73]
  wire [63:0] _GEN_1 = {{32'd0}, _io_out_bits_res_T_60}; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_82 = _io_out_bits_res_T_81 | _GEN_1; // @[Mux.scala 27:73]
  wire [63:0] _GEN_2 = {{32'd0}, _io_out_bits_res_T_61}; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_83 = _io_out_bits_res_T_82 | _GEN_2; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_84 = _io_out_bits_res_T_83 | _io_out_bits_res_T_62; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_85 = _io_out_bits_res_T_84 | _io_out_bits_res_T_63; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_86 = _io_out_bits_res_T_85 | _io_out_bits_res_T_64; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_87 = _io_out_bits_res_T_86 | _io_out_bits_res_T_65; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_88 = _io_out_bits_res_T_87 | _io_out_bits_res_T_66; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_89 = _io_out_bits_res_T_88 | _io_out_bits_res_T_67; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_90 = _io_out_bits_res_T_89 | _io_out_bits_res_T_68; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_91 = _io_out_bits_res_T_90 | _io_out_bits_res_T_69; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_92 = _io_out_bits_res_T_91 | _io_out_bits_res_T_70; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_93 = _io_out_bits_res_T_92 | _io_out_bits_res_T_71; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_94 = _io_out_bits_res_T_93 | _io_out_bits_res_T_72; // @[Mux.scala 27:73]
  wire [63:0] _io_out_bits_res_T_95 = _io_out_bits_res_T_94 | _io_out_bits_res_T_73; // @[Mux.scala 27:73]
  wire  _io_in_ready_T = is_div ? my_div_io_in_ready : io_in_valid; // @[Alu.scala 132:57]
  wire  _io_out_valid_T = io_in_ready & io_in_valid; // @[Decoupled.scala 52:35]
  wire  _io_out_valid_T_1 = is_div ? my_div_io_out_valid : _io_out_valid_T; // @[Alu.scala 133:57]
  ysyx_22051110_MultUnit my_mul ( // @[Alu.scala 65:24]
    .clock(my_mul_clock),
    .reset(my_mul_reset),
    .io_in_ready(my_mul_io_in_ready),
    .io_in_valid(my_mul_io_in_valid),
    .io_in_bits_flush(my_mul_io_in_bits_flush),
    .io_in_bits_mulw(my_mul_io_in_bits_mulw),
    .io_in_bits_mul_signed(my_mul_io_in_bits_mul_signed),
    .io_in_bits_multiplicand(my_mul_io_in_bits_multiplicand),
    .io_in_bits_multiplier(my_mul_io_in_bits_multiplier),
    .io_out_valid(my_mul_io_out_valid),
    .io_out_bits_result_hi(my_mul_io_out_bits_result_hi),
    .io_out_bits_result_lo(my_mul_io_out_bits_result_lo)
  );
  ysyx_22051110_DivUnit my_div ( // @[Alu.scala 88:24]
    .clock(my_div_clock),
    .reset(my_div_reset),
    .io_in_ready(my_div_io_in_ready),
    .io_in_valid(my_div_io_in_valid),
    .io_in_bits_flush(my_div_io_in_bits_flush),
    .io_in_bits_divw(my_div_io_in_bits_divw),
    .io_in_bits_div_signed(my_div_io_in_bits_div_signed),
    .io_in_bits_dividend(my_div_io_in_bits_dividend),
    .io_in_bits_divisor(my_div_io_in_bits_divisor),
    .io_out_valid(my_div_io_out_valid),
    .io_out_bits_quotient(my_div_io_out_bits_quotient),
    .io_out_bits_reminder(my_div_io_out_bits_reminder)
  );
  assign io_in_ready = is_mul ? my_mul_io_in_ready : _io_in_ready_T; // @[Alu.scala 132:24]
  assign io_out_valid = is_mul ? my_mul_io_out_valid : _io_out_valid_T_1; // @[Alu.scala 133:24]
  assign io_out_bits_res = _io_out_bits_res_T_95 | _io_out_bits_res_T_74; // @[Mux.scala 27:73]
  assign io_out_bits_cout = add_res[64]; // @[Alu.scala 54:36]
  assign io_out_bits_overflow = io_in_bits_alu_op[0] ? _io_out_bits_overflow_T_9 : _io_out_bits_overflow_T_16; // @[Alu.scala 55:32]
  assign my_mul_clock = clock;
  assign my_mul_reset = reset;
  assign my_mul_io_in_valid = io_in_valid & is_mul; // @[Alu.scala 66:51]
  assign my_mul_io_in_bits_flush = io_in_bits_alu_flush; // @[Alu.scala 67:36]
  assign my_mul_io_in_bits_mulw = io_in_bits_alu_op[14]; // @[Alu.scala 68:56]
  assign my_mul_io_in_bits_mul_signed = io_in_bits_alu_op[13] ? 2'h2 : _my_mul_io_in_bits_mul_signed_T_4; // @[Alu.scala 69:42]
  assign my_mul_io_in_bits_multiplicand = io_in_bits_src1; // @[Alu.scala 71:36]
  assign my_mul_io_in_bits_multiplier = io_in_bits_src2; // @[Alu.scala 72:36]
  assign my_div_clock = clock;
  assign my_div_reset = reset;
  assign my_div_io_in_valid = io_in_valid & is_div; // @[Alu.scala 89:49]
  assign my_div_io_in_bits_flush = io_in_bits_alu_flush; // @[Alu.scala 90:34]
  assign my_div_io_in_bits_divw = _my_div_io_in_bits_divw_T_4 | io_in_bits_alu_op[22]; // @[Alu.scala 92:59]
  assign my_div_io_in_bits_div_signed = _my_div_io_in_bits_div_signed_T_4 | io_in_bits_alu_op[21]; // @[Alu.scala 94:59]
  assign my_div_io_in_bits_dividend = io_in_bits_src1; // @[Alu.scala 95:34]
  assign my_div_io_in_bits_divisor = io_in_bits_src2; // @[Alu.scala 96:34]
endmodule
module ysyx_22051110_Ex_stage(
  input         clock,
  input         reset,
  output        io_id2ex_ready,
  input         io_id2ex_valid,
  input  [22:0] io_id2ex_bits_alu_op,
  input         io_id2ex_bits_src1_sel,
  input         io_id2ex_bits_src2_sel,
  input  [8:0]  io_id2ex_bits_br_type,
  input         io_id2ex_bits_gr_we,
  input         io_id2ex_bits_wb_sel,
  input         io_id2ex_bits_mem_en,
  input         io_id2ex_bits_mem_wr,
  input  [6:0]  io_id2ex_bits_mem_type,
  input         io_id2ex_bits_rv64w,
  input  [2:0]  io_id2ex_bits_ex_sel,
  input  [2:0]  io_id2ex_bits_csr_op,
  input  [2:0]  io_id2ex_bits_exc_type,
  input         io_id2ex_bits_op_muldiv,
  input         io_id2ex_bits_is_fencei,
  input  [4:0]  io_id2ex_bits_dest,
  input  [31:0] io_id2ex_bits_pc,
  input  [63:0] io_id2ex_bits_rs1,
  input  [63:0] io_id2ex_bits_rs2,
  input  [63:0] io_id2ex_bits_imm,
  input  [63:0] io_id2ex_bits_mem_wdata,
  input  [11:0] io_id2ex_bits_csr_num,
  input         io_ex2mem_ready,
  output        io_ex2mem_valid,
  output [31:0] io_ex2mem_bits_pc,
  output        io_ex2mem_bits_gr_we,
  output [4:0]  io_ex2mem_bits_dest,
  output        io_ex2mem_bits_wb_sel,
  output        io_ex2mem_bits_mem_en,
  output        io_ex2mem_bits_mem_wr,
  output [6:0]  io_ex2mem_bits_mem_type,
  output [2:0]  io_ex2mem_bits_csr_op,
  output [2:0]  io_ex2mem_bits_exc_type,
  output        io_ex2mem_bits_is_fencei,
  output [63:0] io_ex2mem_bits_result,
  output [63:0] io_ex2mem_bits_mem_wdata,
  output [11:0] io_ex2mem_bits_csr_num,
  output [63:0] io_ex2mem_bits_rs1,
  output [31:0] io_ex2mem_bits_br_br_target,
  output        io_ex2mem_bits_br_br_en,
  input         io_exc_flush,
  input         io_br_flush,
  output        io_es_forward_valid,
  output        io_es_forward_bits_en,
  output [4:0]  io_es_forward_bits_dest,
  output [63:0] io_es_forward_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [63:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [63:0] _RAND_21;
  reg [63:0] _RAND_22;
  reg [63:0] _RAND_23;
  reg [63:0] _RAND_24;
  reg [31:0] _RAND_25;
`endif // RANDOMIZE_REG_INIT
  wire  my_alu_clock; // @[Ex_stage.scala 22:28]
  wire  my_alu_reset; // @[Ex_stage.scala 22:28]
  wire  my_alu_io_in_ready; // @[Ex_stage.scala 22:28]
  wire  my_alu_io_in_valid; // @[Ex_stage.scala 22:28]
  wire [63:0] my_alu_io_in_bits_src1; // @[Ex_stage.scala 22:28]
  wire [63:0] my_alu_io_in_bits_src2; // @[Ex_stage.scala 22:28]
  wire [22:0] my_alu_io_in_bits_alu_op; // @[Ex_stage.scala 22:28]
  wire  my_alu_io_in_bits_alu_flush; // @[Ex_stage.scala 22:28]
  wire  my_alu_io_out_valid; // @[Ex_stage.scala 22:28]
  wire [63:0] my_alu_io_out_bits_res; // @[Ex_stage.scala 22:28]
  wire  my_alu_io_out_bits_cout; // @[Ex_stage.scala 22:28]
  wire  my_alu_io_out_bits_overflow; // @[Ex_stage.scala 22:28]
  reg  es_valid; // @[Ex_stage.scala 20:29]
  wire  ex_flush = io_exc_flush | io_br_flush; // @[Ex_stage.scala 21:35]
  reg  alu_wait; // @[Ex_stage.scala 23:29]
  reg  alu_buf_en; // @[Ex_stage.scala 24:29]
  reg [63:0] alu_buf; // @[Ex_stage.scala 25:29]
  reg [22:0] ds_es_r_alu_op; // @[Ex_stage.scala 32:31]
  reg  ds_es_r_src1_sel; // @[Ex_stage.scala 32:31]
  reg  ds_es_r_src2_sel; // @[Ex_stage.scala 32:31]
  reg [8:0] ds_es_r_br_type; // @[Ex_stage.scala 32:31]
  reg  ds_es_r_gr_we; // @[Ex_stage.scala 32:31]
  reg  ds_es_r_wb_sel; // @[Ex_stage.scala 32:31]
  reg  ds_es_r_mem_en; // @[Ex_stage.scala 32:31]
  reg  ds_es_r_mem_wr; // @[Ex_stage.scala 32:31]
  reg [6:0] ds_es_r_mem_type; // @[Ex_stage.scala 32:31]
  reg  ds_es_r_rv64w; // @[Ex_stage.scala 32:31]
  reg [2:0] ds_es_r_ex_sel; // @[Ex_stage.scala 32:31]
  reg [2:0] ds_es_r_csr_op; // @[Ex_stage.scala 32:31]
  reg [2:0] ds_es_r_exc_type; // @[Ex_stage.scala 32:31]
  reg  ds_es_r_op_muldiv; // @[Ex_stage.scala 32:31]
  reg  ds_es_r_is_fencei; // @[Ex_stage.scala 32:31]
  reg [4:0] ds_es_r_dest; // @[Ex_stage.scala 32:31]
  reg [31:0] ds_es_r_pc; // @[Ex_stage.scala 32:31]
  reg [63:0] ds_es_r_rs1; // @[Ex_stage.scala 32:31]
  reg [63:0] ds_es_r_rs2; // @[Ex_stage.scala 32:31]
  reg [63:0] ds_es_r_imm; // @[Ex_stage.scala 32:31]
  reg [63:0] ds_es_r_mem_wdata; // @[Ex_stage.scala 32:31]
  reg [11:0] ds_es_r_csr_num; // @[Ex_stage.scala 32:31]
  wire  _T = io_id2ex_ready & io_id2ex_valid; // @[Decoupled.scala 52:35]
  wire [31:0] _alu_res_T_2 = my_alu_io_out_bits_res[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [31:0] _alu_res_T_4 = ds_es_r_rv64w ? _alu_res_T_2 : my_alu_io_out_bits_res[63:32]; // @[Ex_stage.scala 44:44]
  wire [63:0] _alu_res_T_6 = {_alu_res_T_4,my_alu_io_out_bits_res[31:0]}; // @[Cat.scala 33:92]
  wire [63:0] alu_res = alu_buf_en ? alu_buf : _alu_res_T_6; // @[Ex_stage.scala 43:32]
  wire  s1_lt_s2 = my_alu_io_out_bits_overflow ^ alu_res[63]; // @[Ex_stage.scala 48:38]
  wire  s1_ltu_s2 = ~my_alu_io_out_bits_cout; // @[Ex_stage.scala 49:29]
  wire  _T_2 = my_alu_io_in_ready & my_alu_io_in_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_28 = _T_2 & ~my_alu_io_out_valid | alu_wait; // @[Ex_stage.scala 53:64 54:22 23:29]
  wire  _GEN_30 = my_alu_io_out_valid & ~io_ex2mem_ready | alu_buf_en; // @[Ex_stage.scala 58:62 59:24 24:29]
  wire  is_jal = ds_es_r_br_type[7] | ds_es_r_br_type[8]; // @[Ex_stage.scala 67:51]
  wire [31:0] pc_seq = ds_es_r_pc + 32'h4; // @[Ex_stage.scala 69:43]
  wire [63:0] _GEN_34 = {{32'd0}, ds_es_r_pc}; // @[Ex_stage.scala 70:79]
  wire [63:0] _io_ex2mem_bits_br_br_target_T_2 = _GEN_34 + ds_es_r_imm; // @[Ex_stage.scala 70:79]
  wire [63:0] _io_ex2mem_bits_br_br_target_T_3 = is_jal ? {{32'd0}, alu_res[31:0]} : _io_ex2mem_bits_br_br_target_T_2; // @[Ex_stage.scala 70:43]
  wire  _io_ex2mem_bits_br_br_en_T_2 = alu_res == 64'h0; // @[Ex_stage.scala 73:45]
  wire  _io_ex2mem_bits_br_br_en_T_4 = alu_res != 64'h0; // @[Ex_stage.scala 74:45]
  wire  _io_ex2mem_bits_br_br_en_T_7 = ~s1_lt_s2; // @[Ex_stage.scala 76:36]
  wire  _io_ex2mem_bits_br_br_en_T_10 = ~s1_ltu_s2; // @[Ex_stage.scala 78:36]
  wire  _io_ex2mem_bits_br_br_en_T_29 = ds_es_r_br_type[1] & _io_ex2mem_bits_br_br_en_T_2 | ds_es_r_br_type[2] &
    _io_ex2mem_bits_br_br_en_T_4 | ds_es_r_br_type[3] & s1_lt_s2 | ds_es_r_br_type[4] & _io_ex2mem_bits_br_br_en_T_7 |
    ds_es_r_br_type[5] & s1_ltu_s2 | ds_es_r_br_type[6] & _io_ex2mem_bits_br_br_en_T_10 | ds_es_r_br_type[7] |
    ds_es_r_br_type[8]; // @[Mux.scala 27:73]
  wire [63:0] _res_T_5 = ds_es_r_ex_sel[0] ? alu_res : 64'h0; // @[Mux.scala 27:73]
  wire  _res_T_6 = ds_es_r_ex_sel[1] & s1_lt_s2; // @[Mux.scala 27:73]
  wire  _res_T_7 = ds_es_r_ex_sel[2] & s1_ltu_s2; // @[Mux.scala 27:73]
  wire [63:0] _GEN_35 = {{63'd0}, _res_T_6}; // @[Mux.scala 27:73]
  wire [63:0] _res_T_8 = _res_T_5 | _GEN_35; // @[Mux.scala 27:73]
  wire [63:0] _GEN_36 = {{63'd0}, _res_T_7}; // @[Mux.scala 27:73]
  wire [63:0] res = _res_T_8 | _GEN_36; // @[Mux.scala 27:73]
  wire  _es_ready_go_T_2 = ds_es_r_op_muldiv & my_alu_io_out_valid; // @[Ex_stage.scala 114:48]
  wire  es_ready_go = ~ds_es_r_op_muldiv | ex_flush | _es_ready_go_T_2; // @[Ex_stage.scala 113:59]
  ysyx_22051110_Alu my_alu ( // @[Ex_stage.scala 22:28]
    .clock(my_alu_clock),
    .reset(my_alu_reset),
    .io_in_ready(my_alu_io_in_ready),
    .io_in_valid(my_alu_io_in_valid),
    .io_in_bits_src1(my_alu_io_in_bits_src1),
    .io_in_bits_src2(my_alu_io_in_bits_src2),
    .io_in_bits_alu_op(my_alu_io_in_bits_alu_op),
    .io_in_bits_alu_flush(my_alu_io_in_bits_alu_flush),
    .io_out_valid(my_alu_io_out_valid),
    .io_out_bits_res(my_alu_io_out_bits_res),
    .io_out_bits_cout(my_alu_io_out_bits_cout),
    .io_out_bits_overflow(my_alu_io_out_bits_overflow)
  );
  assign io_id2ex_ready = ~es_valid | es_ready_go & io_ex2mem_ready; // @[Ex_stage.scala 115:38]
  assign io_ex2mem_valid = es_valid & es_ready_go; // @[Ex_stage.scala 116:38]
  assign io_ex2mem_bits_pc = ds_es_r_pc; // @[Ex_stage.scala 89:34]
  assign io_ex2mem_bits_gr_we = ds_es_r_gr_we; // @[Ex_stage.scala 91:34]
  assign io_ex2mem_bits_dest = ds_es_r_dest; // @[Ex_stage.scala 92:34]
  assign io_ex2mem_bits_wb_sel = ds_es_r_wb_sel; // @[Ex_stage.scala 93:34]
  assign io_ex2mem_bits_mem_en = ds_es_r_mem_en; // @[Ex_stage.scala 94:34]
  assign io_ex2mem_bits_mem_wr = ds_es_r_mem_wr; // @[Ex_stage.scala 95:34]
  assign io_ex2mem_bits_mem_type = ds_es_r_mem_type; // @[Ex_stage.scala 96:34]
  assign io_ex2mem_bits_csr_op = ds_es_r_csr_op; // @[Ex_stage.scala 98:34]
  assign io_ex2mem_bits_exc_type = ds_es_r_exc_type; // @[Ex_stage.scala 99:34]
  assign io_ex2mem_bits_is_fencei = ds_es_r_is_fencei; // @[Ex_stage.scala 101:34]
  assign io_ex2mem_bits_result = is_jal ? {{32'd0}, pc_seq} : res; // @[Ex_stage.scala 103:40]
  assign io_ex2mem_bits_mem_wdata = ds_es_r_mem_wdata; // @[Ex_stage.scala 97:34]
  assign io_ex2mem_bits_csr_num = ds_es_r_csr_num; // @[Ex_stage.scala 104:34]
  assign io_ex2mem_bits_rs1 = ds_es_r_rs1; // @[Ex_stage.scala 105:34]
  assign io_ex2mem_bits_br_br_target = _io_ex2mem_bits_br_br_target_T_3[31:0]; // @[Ex_stage.scala 70:37]
  assign io_ex2mem_bits_br_br_en = _io_ex2mem_bits_br_br_en_T_29 & es_valid; // @[Ex_stage.scala 81:12]
  assign io_es_forward_valid = io_ex2mem_valid & ~(ds_es_r_mem_en & ~ds_es_r_mem_wr) & ~(|ds_es_r_csr_op); // @[Ex_stage.scala 108:92]
  assign io_es_forward_bits_en = es_valid & io_ex2mem_bits_gr_we; // @[Ex_stage.scala 109:45]
  assign io_es_forward_bits_dest = io_ex2mem_bits_dest; // @[Ex_stage.scala 110:33]
  assign io_es_forward_bits_data = io_ex2mem_bits_result; // @[Ex_stage.scala 111:33]
  assign my_alu_clock = clock;
  assign my_alu_reset = reset;
  assign my_alu_io_in_valid = es_valid & ~alu_wait & ~alu_buf_en; // @[Ex_stage.scala 37:62]
  assign my_alu_io_in_bits_src1 = ds_es_r_src1_sel ? {{32'd0}, ds_es_r_pc} : ds_es_r_rs1; // @[Ex_stage.scala 39:43]
  assign my_alu_io_in_bits_src2 = ds_es_r_src2_sel ? ds_es_r_imm : ds_es_r_rs2; // @[Ex_stage.scala 40:43]
  assign my_alu_io_in_bits_alu_op = ds_es_r_alu_op; // @[Ex_stage.scala 41:37]
  assign my_alu_io_in_bits_alu_flush = io_exc_flush | io_br_flush; // @[Ex_stage.scala 21:35]
  always @(posedge clock) begin
    if (reset) begin // @[Ex_stage.scala 20:29]
      es_valid <= 1'h0; // @[Ex_stage.scala 20:29]
    end else if (ex_flush) begin // @[Ex_stage.scala 27:23]
      es_valid <= 1'h0; // @[Ex_stage.scala 28:22]
    end else if (io_id2ex_ready) begin // @[Ex_stage.scala 29:36]
      es_valid <= io_id2ex_valid; // @[Ex_stage.scala 30:22]
    end
    if (reset) begin // @[Ex_stage.scala 23:29]
      alu_wait <= 1'h0; // @[Ex_stage.scala 23:29]
    end else if (ex_flush | my_alu_io_out_valid) begin // @[Ex_stage.scala 51:47]
      alu_wait <= 1'h0; // @[Ex_stage.scala 52:22]
    end else begin
      alu_wait <= _GEN_28;
    end
    if (reset) begin // @[Ex_stage.scala 24:29]
      alu_buf_en <= 1'h0; // @[Ex_stage.scala 24:29]
    end else if (ex_flush | alu_buf_en & io_ex2mem_ready) begin // @[Ex_stage.scala 56:58]
      alu_buf_en <= 1'h0; // @[Ex_stage.scala 57:24]
    end else begin
      alu_buf_en <= _GEN_30;
    end
    if (reset) begin // @[Ex_stage.scala 25:29]
      alu_buf <= 64'h0; // @[Ex_stage.scala 25:29]
    end else if (!(ex_flush | alu_buf_en & io_ex2mem_ready)) begin // @[Ex_stage.scala 56:58]
      if (my_alu_io_out_valid & ~io_ex2mem_ready) begin // @[Ex_stage.scala 58:62]
        if (!(alu_buf_en)) begin // @[Ex_stage.scala 43:32]
          alu_buf <= _alu_res_T_6;
        end
      end
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_alu_op <= 23'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_alu_op <= io_id2ex_bits_alu_op; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_src1_sel <= 1'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_src1_sel <= io_id2ex_bits_src1_sel; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_src2_sel <= 1'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_src2_sel <= io_id2ex_bits_src2_sel; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_br_type <= 9'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_br_type <= io_id2ex_bits_br_type; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_gr_we <= 1'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_gr_we <= io_id2ex_bits_gr_we; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_wb_sel <= 1'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_wb_sel <= io_id2ex_bits_wb_sel; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_mem_en <= 1'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_mem_en <= io_id2ex_bits_mem_en; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_mem_wr <= 1'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_mem_wr <= io_id2ex_bits_mem_wr; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_mem_type <= 7'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_mem_type <= io_id2ex_bits_mem_type; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_rv64w <= 1'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_rv64w <= io_id2ex_bits_rv64w; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_ex_sel <= 3'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_ex_sel <= io_id2ex_bits_ex_sel; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_csr_op <= 3'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_csr_op <= io_id2ex_bits_csr_op; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_exc_type <= 3'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_exc_type <= io_id2ex_bits_exc_type; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_op_muldiv <= 1'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_op_muldiv <= io_id2ex_bits_op_muldiv; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_is_fencei <= 1'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_is_fencei <= io_id2ex_bits_is_fencei; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_dest <= 5'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_dest <= io_id2ex_bits_dest; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_pc <= 32'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_pc <= io_id2ex_bits_pc; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_rs1 <= 64'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_rs1 <= io_id2ex_bits_rs1; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_rs2 <= 64'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_rs2 <= io_id2ex_bits_rs2; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_imm <= 64'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_imm <= io_id2ex_bits_imm; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_mem_wdata <= 64'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_mem_wdata <= io_id2ex_bits_mem_wdata; // @[Ex_stage.scala 34:21]
    end
    if (reset) begin // @[Ex_stage.scala 32:31]
      ds_es_r_csr_num <= 12'h0; // @[Ex_stage.scala 32:31]
    end else if (_T) begin // @[Ex_stage.scala 33:28]
      ds_es_r_csr_num <= io_id2ex_bits_csr_num; // @[Ex_stage.scala 34:21]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  es_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  alu_wait = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  alu_buf_en = _RAND_2[0:0];
  _RAND_3 = {2{`RANDOM}};
  alu_buf = _RAND_3[63:0];
  _RAND_4 = {1{`RANDOM}};
  ds_es_r_alu_op = _RAND_4[22:0];
  _RAND_5 = {1{`RANDOM}};
  ds_es_r_src1_sel = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  ds_es_r_src2_sel = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  ds_es_r_br_type = _RAND_7[8:0];
  _RAND_8 = {1{`RANDOM}};
  ds_es_r_gr_we = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  ds_es_r_wb_sel = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  ds_es_r_mem_en = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  ds_es_r_mem_wr = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  ds_es_r_mem_type = _RAND_12[6:0];
  _RAND_13 = {1{`RANDOM}};
  ds_es_r_rv64w = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  ds_es_r_ex_sel = _RAND_14[2:0];
  _RAND_15 = {1{`RANDOM}};
  ds_es_r_csr_op = _RAND_15[2:0];
  _RAND_16 = {1{`RANDOM}};
  ds_es_r_exc_type = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  ds_es_r_op_muldiv = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  ds_es_r_is_fencei = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  ds_es_r_dest = _RAND_19[4:0];
  _RAND_20 = {1{`RANDOM}};
  ds_es_r_pc = _RAND_20[31:0];
  _RAND_21 = {2{`RANDOM}};
  ds_es_r_rs1 = _RAND_21[63:0];
  _RAND_22 = {2{`RANDOM}};
  ds_es_r_rs2 = _RAND_22[63:0];
  _RAND_23 = {2{`RANDOM}};
  ds_es_r_imm = _RAND_23[63:0];
  _RAND_24 = {2{`RANDOM}};
  ds_es_r_mem_wdata = _RAND_24[63:0];
  _RAND_25 = {1{`RANDOM}};
  ds_es_r_csr_num = _RAND_25[11:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_Mem_stage(
  input         clock,
  input         reset,
  output        io_ex2mem_ready,
  input         io_ex2mem_valid,
  input  [31:0] io_ex2mem_bits_pc,
  input         io_ex2mem_bits_gr_we,
  input  [4:0]  io_ex2mem_bits_dest,
  input         io_ex2mem_bits_wb_sel,
  input         io_ex2mem_bits_mem_en,
  input         io_ex2mem_bits_mem_wr,
  input  [6:0]  io_ex2mem_bits_mem_type,
  input  [2:0]  io_ex2mem_bits_csr_op,
  input  [2:0]  io_ex2mem_bits_exc_type,
  input         io_ex2mem_bits_is_fencei,
  input  [63:0] io_ex2mem_bits_result,
  input  [63:0] io_ex2mem_bits_mem_wdata,
  input  [11:0] io_ex2mem_bits_csr_num,
  input  [63:0] io_ex2mem_bits_rs1,
  input  [31:0] io_ex2mem_bits_br_br_target,
  input         io_ex2mem_bits_br_br_en,
  output        io_mem2wb_valid,
  output [31:0] io_mem2wb_bits_pc,
  output        io_mem2wb_bits_gr_we,
  output [2:0]  io_mem2wb_bits_csr_op,
  output [2:0]  io_mem2wb_bits_exc_type,
  output [4:0]  io_mem2wb_bits_dest,
  output [63:0] io_mem2wb_bits_result,
  output [11:0] io_mem2wb_bits_csr_num,
  output [63:0] io_mem2wb_bits_rs1,
  output [31:0] io_branch_br_target,
  output        io_branch_br_en,
  input         io_exc_flush,
  input         io_data_mem_req_ready,
  output        io_data_mem_req_valid,
  output        io_data_mem_req_bits_wr,
  output [31:0] io_data_mem_req_bits_addr,
  output [1:0]  io_data_mem_req_bits_size,
  output [63:0] io_data_mem_req_bits_wdata,
  output [7:0]  io_data_mem_req_bits_wstrb,
  output        io_data_mem_req_bits_mthrough,
  output        io_data_mem_req_bits_fencei,
  input  [63:0] io_data_mem_ret_rdata,
  input         io_data_mem_ret_valid,
  output        io_ms_forward_valid,
  output        io_ms_forward_bits_en,
  output [4:0]  io_ms_forward_bits_dest,
  output [63:0] io_ms_forward_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [63:0] _RAND_11;
  reg [63:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [63:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] mm_io_addr_in; // @[Mem_stage.scala 101:44]
  wire  mm_io_mthrough; // @[Mem_stage.scala 101:44]
  reg  ms_valid; // @[Mem_stage.scala 26:31]
  reg [31:0] es_ms_r_pc; // @[Mem_stage.scala 27:31]
  reg  es_ms_r_gr_we; // @[Mem_stage.scala 27:31]
  reg [4:0] es_ms_r_dest; // @[Mem_stage.scala 27:31]
  reg  es_ms_r_wb_sel; // @[Mem_stage.scala 27:31]
  reg  es_ms_r_mem_en; // @[Mem_stage.scala 27:31]
  reg  es_ms_r_mem_wr; // @[Mem_stage.scala 27:31]
  reg [6:0] es_ms_r_mem_type; // @[Mem_stage.scala 27:31]
  reg [2:0] es_ms_r_csr_op; // @[Mem_stage.scala 27:31]
  reg [2:0] es_ms_r_exc_type; // @[Mem_stage.scala 27:31]
  reg  es_ms_r_is_fencei; // @[Mem_stage.scala 27:31]
  reg [63:0] es_ms_r_result; // @[Mem_stage.scala 27:31]
  reg [63:0] es_ms_r_mem_wdata; // @[Mem_stage.scala 27:31]
  reg [11:0] es_ms_r_csr_num; // @[Mem_stage.scala 27:31]
  reg [63:0] es_ms_r_rs1; // @[Mem_stage.scala 27:31]
  reg [31:0] es_ms_r_br_br_target; // @[Mem_stage.scala 27:31]
  reg  es_ms_r_br_br_en; // @[Mem_stage.scala 27:31]
  wire  _T = io_ex2mem_ready & io_ex2mem_valid; // @[Decoupled.scala 52:35]
  wire [2:0] offset = es_ms_r_result[2:0]; // @[Mem_stage.scala 35:38]
  wire [1:0] _wmask_b_T_1 = 3'h1 == offset ? 2'h2 : 2'h1; // @[Mux.scala 81:58]
  wire [2:0] _wmask_b_T_3 = 3'h2 == offset ? 3'h4 : {{1'd0}, _wmask_b_T_1}; // @[Mux.scala 81:58]
  wire [3:0] _wmask_b_T_5 = 3'h3 == offset ? 4'h8 : {{1'd0}, _wmask_b_T_3}; // @[Mux.scala 81:58]
  wire [4:0] _wmask_b_T_7 = 3'h4 == offset ? 5'h10 : {{1'd0}, _wmask_b_T_5}; // @[Mux.scala 81:58]
  wire [5:0] _wmask_b_T_9 = 3'h5 == offset ? 6'h20 : {{1'd0}, _wmask_b_T_7}; // @[Mux.scala 81:58]
  wire [6:0] _wmask_b_T_11 = 3'h6 == offset ? 7'h40 : {{1'd0}, _wmask_b_T_9}; // @[Mux.scala 81:58]
  wire [7:0] wmask_b = 3'h7 == offset ? 8'h80 : {{1'd0}, _wmask_b_T_11}; // @[Mux.scala 81:58]
  wire [3:0] _wmask_h_T_2 = 2'h1 == offset[2:1] ? 4'hc : 4'h3; // @[Mux.scala 81:58]
  wire [5:0] _wmask_h_T_4 = 2'h2 == offset[2:1] ? 6'h30 : {{2'd0}, _wmask_h_T_2}; // @[Mux.scala 81:58]
  wire [7:0] wmask_h = 2'h3 == offset[2:1] ? 8'hc0 : {{2'd0}, _wmask_h_T_4}; // @[Mux.scala 81:58]
  wire [7:0] wmask_w = offset[2] ? 8'hf0 : 8'hf; // @[Mux.scala 81:58]
  wire [7:0] _wmask_T_4 = es_ms_r_mem_type[0] ? wmask_b : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _wmask_T_5 = es_ms_r_mem_type[1] ? wmask_h : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _wmask_T_6 = es_ms_r_mem_type[2] ? wmask_w : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _wmask_T_7 = es_ms_r_mem_type[6] ? 8'hff : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _wmask_T_8 = _wmask_T_4 | _wmask_T_5; // @[Mux.scala 27:73]
  wire [7:0] _wmask_T_9 = _wmask_T_8 | _wmask_T_6; // @[Mux.scala 27:73]
  wire [63:0] _wdata_T_4 = {es_ms_r_mem_wdata[7:0],es_ms_r_mem_wdata[7:0],es_ms_r_mem_wdata[7:0],es_ms_r_mem_wdata[7:0],
    es_ms_r_mem_wdata[7:0],es_ms_r_mem_wdata[7:0],es_ms_r_mem_wdata[7:0],es_ms_r_mem_wdata[7:0]}; // @[Cat.scala 33:92]
  wire [63:0] _wdata_T_8 = {es_ms_r_mem_wdata[15:0],es_ms_r_mem_wdata[15:0],es_ms_r_mem_wdata[15:0],es_ms_r_mem_wdata[15
    :0]}; // @[Cat.scala 33:92]
  wire [63:0] _wdata_T_11 = {es_ms_r_mem_wdata[31:0],es_ms_r_mem_wdata[31:0]}; // @[Cat.scala 33:92]
  wire [63:0] _wdata_T_13 = es_ms_r_mem_type[0] ? _wdata_T_4 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _wdata_T_14 = es_ms_r_mem_type[1] ? _wdata_T_8 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _wdata_T_15 = es_ms_r_mem_type[2] ? _wdata_T_11 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _wdata_T_16 = es_ms_r_mem_type[6] ? es_ms_r_mem_wdata : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _wdata_T_17 = _wdata_T_13 | _wdata_T_14; // @[Mux.scala 27:73]
  wire [63:0] _wdata_T_18 = _wdata_T_17 | _wdata_T_15; // @[Mux.scala 27:73]
  reg [2:0] ms_state; // @[Mem_stage.scala 70:29]
  wire  _ms_state_T_1 = io_data_mem_req_ready & io_data_mem_req_valid; // @[Decoupled.scala 52:35]
  wire [2:0] _ms_state_T_2 = _ms_state_T_1 ? 3'h4 : 3'h1; // @[Mem_stage.scala 73:58]
  wire [1:0] _ms_state_T_4 = _ms_state_T_1 ? 2'h2 : 2'h1; // @[Mem_stage.scala 74:58]
  wire [2:0] _ms_state_T_5 = io_exc_flush ? _ms_state_T_2 : {{1'd0}, _ms_state_T_4}; // @[Mem_stage.scala 73:44]
  wire [2:0] _ms_state_T_7 = io_data_mem_ret_valid ? 3'h1 : 3'h4; // @[Mem_stage.scala 75:58]
  wire [1:0] _ms_state_T_8 = io_data_mem_ret_valid ? 2'h1 : 2'h2; // @[Mem_stage.scala 76:58]
  wire [2:0] _ms_state_T_9 = io_exc_flush ? _ms_state_T_7 : {{1'd0}, _ms_state_T_8}; // @[Mem_stage.scala 75:44]
  wire [2:0] _ms_state_T_12 = ms_state[0] ? _ms_state_T_5 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _ms_state_T_13 = ms_state[1] ? _ms_state_T_9 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _ms_state_T_14 = ms_state[2] ? _ms_state_T_7 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _ms_state_T_15 = _ms_state_T_12 | _ms_state_T_13; // @[Mux.scala 27:73]
  wire [2:0] _ms_state_T_16 = _ms_state_T_15 | _ms_state_T_14; // @[Mux.scala 27:73]
  wire  ms_mem_en = es_ms_r_mem_en & ~io_exc_flush & ms_valid; // @[Mem_stage.scala 84:50]
  wire [1:0] _io_data_mem_req_bits_size_T_9 = es_ms_r_mem_type[2] ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _io_data_mem_req_bits_size_T_12 = es_ms_r_mem_type[5] ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _io_data_mem_req_bits_size_T_13 = es_ms_r_mem_type[6] ? 2'h3 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_23 = {{1'd0}, es_ms_r_mem_type[1]}; // @[Mux.scala 27:73]
  wire [1:0] _io_data_mem_req_bits_size_T_15 = _GEN_23 | _io_data_mem_req_bits_size_T_9; // @[Mux.scala 27:73]
  wire [1:0] _GEN_24 = {{1'd0}, es_ms_r_mem_type[4]}; // @[Mux.scala 27:73]
  wire [1:0] _io_data_mem_req_bits_size_T_17 = _io_data_mem_req_bits_size_T_15 | _GEN_24; // @[Mux.scala 27:73]
  wire [1:0] _io_data_mem_req_bits_size_T_18 = _io_data_mem_req_bits_size_T_17 | _io_data_mem_req_bits_size_T_12; // @[Mux.scala 27:73]
  wire  ms_mem_ok = io_data_mem_ret_valid & ms_state[1] & ms_mem_en; // @[Mem_stage.scala 105:60]
  wire  ms_ready_go = ~ms_mem_en | ms_mem_ok; // @[Mem_stage.scala 106:34]
  wire [7:0] _rdata_b_T_9 = 3'h1 == offset ? io_data_mem_ret_rdata[15:8] : io_data_mem_ret_rdata[7:0]; // @[Mux.scala 81:58]
  wire [7:0] _rdata_b_T_11 = 3'h2 == offset ? io_data_mem_ret_rdata[23:16] : _rdata_b_T_9; // @[Mux.scala 81:58]
  wire [7:0] _rdata_b_T_13 = 3'h3 == offset ? io_data_mem_ret_rdata[31:24] : _rdata_b_T_11; // @[Mux.scala 81:58]
  wire [7:0] _rdata_b_T_15 = 3'h4 == offset ? io_data_mem_ret_rdata[39:32] : _rdata_b_T_13; // @[Mux.scala 81:58]
  wire [7:0] _rdata_b_T_17 = 3'h5 == offset ? io_data_mem_ret_rdata[47:40] : _rdata_b_T_15; // @[Mux.scala 81:58]
  wire [7:0] _rdata_b_T_19 = 3'h6 == offset ? io_data_mem_ret_rdata[55:48] : _rdata_b_T_17; // @[Mux.scala 81:58]
  wire [7:0] rdata_b = 3'h7 == offset ? io_data_mem_ret_rdata[63:56] : _rdata_b_T_19; // @[Mux.scala 81:58]
  wire [15:0] _rdata_h_T_5 = 3'h0 == offset ? io_data_mem_ret_rdata[15:0] : 16'h0; // @[Mux.scala 81:58]
  wire [15:0] _rdata_h_T_7 = 3'h2 == offset ? io_data_mem_ret_rdata[31:16] : _rdata_h_T_5; // @[Mux.scala 81:58]
  wire [15:0] _rdata_h_T_9 = 3'h4 == offset ? io_data_mem_ret_rdata[47:32] : _rdata_h_T_7; // @[Mux.scala 81:58]
  wire [15:0] rdata_h = 3'h6 == offset ? io_data_mem_ret_rdata[63:48] : _rdata_h_T_9; // @[Mux.scala 81:58]
  wire [31:0] rdata_w = offset[2] ? io_data_mem_ret_rdata[63:32] : io_data_mem_ret_rdata[31:0]; // @[Mem_stage.scala 132:22]
  wire [55:0] _rdata_T_3 = rdata_b[7] ? 56'hffffffffffffff : 56'h0; // @[Bitwise.scala 77:12]
  wire [63:0] _rdata_T_5 = {_rdata_T_3,rdata_b}; // @[Cat.scala 33:92]
  wire [47:0] _rdata_T_9 = rdata_h[15] ? 48'hffffffffffff : 48'h0; // @[Bitwise.scala 77:12]
  wire [63:0] _rdata_T_11 = {_rdata_T_9,rdata_h}; // @[Cat.scala 33:92]
  wire [31:0] _rdata_T_15 = rdata_w[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 77:12]
  wire [63:0] _rdata_T_17 = {_rdata_T_15,rdata_w}; // @[Cat.scala 33:92]
  wire [63:0] _rdata_T_21 = {56'h0,rdata_b}; // @[Cat.scala 33:92]
  wire [63:0] _rdata_T_25 = {48'h0,rdata_h}; // @[Cat.scala 33:92]
  wire [63:0] _rdata_T_29 = {32'h0,rdata_w}; // @[Cat.scala 33:92]
  wire [63:0] _rdata_T_31 = es_ms_r_mem_type[0] ? _rdata_T_5 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _rdata_T_32 = es_ms_r_mem_type[1] ? _rdata_T_11 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _rdata_T_33 = es_ms_r_mem_type[2] ? _rdata_T_17 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _rdata_T_34 = es_ms_r_mem_type[3] ? _rdata_T_21 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _rdata_T_35 = es_ms_r_mem_type[4] ? _rdata_T_25 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _rdata_T_36 = es_ms_r_mem_type[5] ? _rdata_T_29 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _rdata_T_37 = es_ms_r_mem_type[6] ? io_data_mem_ret_rdata : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _rdata_T_38 = _rdata_T_31 | _rdata_T_32; // @[Mux.scala 27:73]
  wire [63:0] _rdata_T_39 = _rdata_T_38 | _rdata_T_33; // @[Mux.scala 27:73]
  wire [63:0] _rdata_T_40 = _rdata_T_39 | _rdata_T_34; // @[Mux.scala 27:73]
  wire [63:0] _rdata_T_41 = _rdata_T_40 | _rdata_T_35; // @[Mux.scala 27:73]
  wire [63:0] _rdata_T_42 = _rdata_T_41 | _rdata_T_36; // @[Mux.scala 27:73]
  wire [63:0] rdata = _rdata_T_42 | _rdata_T_37; // @[Mux.scala 27:73]
  ysyx_22051110_MemoryMappingUnit mm ( // @[Mem_stage.scala 101:44]
    .io_addr_in(mm_io_addr_in),
    .io_mthrough(mm_io_mthrough)
  );
  assign io_ex2mem_ready = ~ms_valid | ms_ready_go; // @[Mem_stage.scala 162:46]
  assign io_mem2wb_valid = ms_valid & ms_ready_go; // @[Mem_stage.scala 144:45]
  assign io_mem2wb_bits_pc = es_ms_r_pc; // @[Mem_stage.scala 152:33]
  assign io_mem2wb_bits_gr_we = es_ms_r_gr_we; // @[Mem_stage.scala 146:33]
  assign io_mem2wb_bits_csr_op = es_ms_r_csr_op; // @[Mem_stage.scala 147:33]
  assign io_mem2wb_bits_exc_type = es_ms_r_exc_type; // @[Mem_stage.scala 148:33]
  assign io_mem2wb_bits_dest = es_ms_r_dest; // @[Mem_stage.scala 153:33]
  assign io_mem2wb_bits_result = es_ms_r_wb_sel ? rdata : es_ms_r_result; // @[Mem_stage.scala 154:39]
  assign io_mem2wb_bits_csr_num = es_ms_r_csr_num; // @[Mem_stage.scala 155:33]
  assign io_mem2wb_bits_rs1 = es_ms_r_rs1; // @[Mem_stage.scala 156:33]
  assign io_branch_br_target = es_ms_r_br_br_target; // @[Mem_stage.scala 160:33]
  assign io_branch_br_en = es_ms_r_br_br_en & io_mem2wb_valid; // @[Mem_stage.scala 159:53]
  assign io_data_mem_req_valid = ms_mem_en & ms_state[0]; // @[Mem_stage.scala 85:48]
  assign io_data_mem_req_bits_wr = es_ms_r_mem_wr; // @[Mem_stage.scala 86:35]
  assign io_data_mem_req_bits_addr = es_ms_r_result[31:0]; // @[Mem_stage.scala 34:38]
  assign io_data_mem_req_bits_size = _io_data_mem_req_bits_size_T_18 | _io_data_mem_req_bits_size_T_13; // @[Mux.scala 27:73]
  assign io_data_mem_req_bits_wdata = _wdata_T_18 | _wdata_T_16; // @[Mux.scala 27:73]
  assign io_data_mem_req_bits_wstrb = _wmask_T_9 | _wmask_T_7; // @[Mux.scala 27:73]
  assign io_data_mem_req_bits_mthrough = mm_io_mthrough; // @[Mem_stage.scala 103:35]
  assign io_data_mem_req_bits_fencei = es_ms_r_is_fencei; // @[Mem_stage.scala 90:35]
  assign io_ms_forward_valid = io_mem2wb_valid & ~(|es_ms_r_csr_op); // @[Mem_stage.scala 169:48]
  assign io_ms_forward_bits_en = ms_valid & es_ms_r_gr_we; // @[Mem_stage.scala 170:41]
  assign io_ms_forward_bits_dest = io_mem2wb_bits_dest; // @[Mem_stage.scala 171:29]
  assign io_ms_forward_bits_data = io_mem2wb_bits_result; // @[Mem_stage.scala 172:29]
  assign mm_io_addr_in = io_data_mem_req_bits_addr; // @[Mem_stage.scala 102:35]
  always @(posedge clock) begin
    if (reset) begin // @[Mem_stage.scala 26:31]
      ms_valid <= 1'h0; // @[Mem_stage.scala 26:31]
    end else if (io_exc_flush | io_branch_br_en) begin // @[Mem_stage.scala 163:39]
      ms_valid <= 1'h0; // @[Mem_stage.scala 164:18]
    end else if (io_ex2mem_ready) begin // @[Mem_stage.scala 165:33]
      ms_valid <= io_ex2mem_valid; // @[Mem_stage.scala 166:18]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_pc <= 32'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_pc <= io_ex2mem_bits_pc; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_gr_we <= 1'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_gr_we <= io_ex2mem_bits_gr_we; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_dest <= 5'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_dest <= io_ex2mem_bits_dest; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_wb_sel <= 1'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_wb_sel <= io_ex2mem_bits_wb_sel; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_mem_en <= 1'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_mem_en <= io_ex2mem_bits_mem_en; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_mem_wr <= 1'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_mem_wr <= io_ex2mem_bits_mem_wr; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_mem_type <= 7'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_mem_type <= io_ex2mem_bits_mem_type; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_csr_op <= 3'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_csr_op <= io_ex2mem_bits_csr_op; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_exc_type <= 3'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_exc_type <= io_ex2mem_bits_exc_type; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_is_fencei <= 1'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_is_fencei <= io_ex2mem_bits_is_fencei; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_result <= 64'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_result <= io_ex2mem_bits_result; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_mem_wdata <= 64'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_mem_wdata <= io_ex2mem_bits_mem_wdata; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_csr_num <= 12'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_csr_num <= io_ex2mem_bits_csr_num; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_rs1 <= 64'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_rs1 <= io_ex2mem_bits_rs1; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_br_br_target <= 32'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_br_br_target <= io_ex2mem_bits_br_br_target; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 27:31]
      es_ms_r_br_br_en <= 1'h0; // @[Mem_stage.scala 27:31]
    end else if (_T) begin // @[Mem_stage.scala 28:26]
      es_ms_r_br_br_en <= io_ex2mem_bits_br_br_en; // @[Mem_stage.scala 29:21]
    end
    if (reset) begin // @[Mem_stage.scala 70:29]
      ms_state <= 3'h1; // @[Mem_stage.scala 70:29]
    end else begin
      ms_state <= _ms_state_T_16; // @[Mem_stage.scala 72:14]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ms_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  es_ms_r_pc = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  es_ms_r_gr_we = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  es_ms_r_dest = _RAND_3[4:0];
  _RAND_4 = {1{`RANDOM}};
  es_ms_r_wb_sel = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  es_ms_r_mem_en = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  es_ms_r_mem_wr = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  es_ms_r_mem_type = _RAND_7[6:0];
  _RAND_8 = {1{`RANDOM}};
  es_ms_r_csr_op = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  es_ms_r_exc_type = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  es_ms_r_is_fencei = _RAND_10[0:0];
  _RAND_11 = {2{`RANDOM}};
  es_ms_r_result = _RAND_11[63:0];
  _RAND_12 = {2{`RANDOM}};
  es_ms_r_mem_wdata = _RAND_12[63:0];
  _RAND_13 = {1{`RANDOM}};
  es_ms_r_csr_num = _RAND_13[11:0];
  _RAND_14 = {2{`RANDOM}};
  es_ms_r_rs1 = _RAND_14[63:0];
  _RAND_15 = {1{`RANDOM}};
  es_ms_r_br_br_target = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  es_ms_r_br_br_en = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  ms_state = _RAND_17[2:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_Wb_stage(
  input         clock,
  input         reset,
  output        io_mem2wb_ready,
  input         io_mem2wb_valid,
  input  [31:0] io_mem2wb_bits_pc,
  input         io_mem2wb_bits_gr_we,
  input  [2:0]  io_mem2wb_bits_csr_op,
  input  [2:0]  io_mem2wb_bits_exc_type,
  input  [4:0]  io_mem2wb_bits_dest,
  input  [63:0] io_mem2wb_bits_result,
  input  [11:0] io_mem2wb_bits_csr_num,
  input  [63:0] io_mem2wb_bits_rs1,
  output        io_wb2rf_rf_we,
  output [4:0]  io_wb2rf_waddr,
  output [63:0] io_wb2rf_wdata,
  output        io_exc_br_exc_br,
  output [31:0] io_exc_br_exc_target,
  output        io_csr_op_csr_en,
  output [2:0]  io_csr_op_csr_op,
  output [11:0] io_csr_op_csr_num,
  output [63:0] io_csr_op_csr_wdata,
  input  [63:0] io_csr_op_csr_old,
  output        io_csr_exc_ecall,
  output        io_csr_exc_mret,
  output [29:0] io_csr_exc_epc,
  output [63:0] io_csr_exc_exc_code,
  input         io_csr_exc_intr_t,
  input  [31:0] io_csr_exc_mret_addr,
  input  [31:0] io_csr_out_mtvec,
  output        io_ws_forward_valid,
  output        io_ws_forward_bits_en,
  output [4:0]  io_ws_forward_bits_dest,
  output [63:0] io_ws_forward_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [63:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [63:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  reg  ws_valid; // @[Wb_stage.scala 15:31]
  reg [31:0] ms_ws_r_pc; // @[Wb_stage.scala 16:31]
  reg  ms_ws_r_gr_we; // @[Wb_stage.scala 16:31]
  reg [2:0] ms_ws_r_csr_op; // @[Wb_stage.scala 16:31]
  reg [2:0] ms_ws_r_exc_type; // @[Wb_stage.scala 16:31]
  reg [4:0] ms_ws_r_dest; // @[Wb_stage.scala 16:31]
  reg [63:0] ms_ws_r_result; // @[Wb_stage.scala 16:31]
  reg [11:0] ms_ws_r_csr_num; // @[Wb_stage.scala 16:31]
  reg [63:0] ms_ws_r_rs1; // @[Wb_stage.scala 16:31]
  wire  has_trap = |ms_ws_r_exc_type & ws_valid | io_csr_exc_intr_t; // @[Wb_stage.scala 17:67]
  wire  _ws_valid_T = ~has_trap; // @[Wb_stage.scala 19:24]
  wire  _T = io_mem2wb_ready & io_mem2wb_valid; // @[Decoupled.scala 52:35]
  wire  _io_exc_br_exc_target_T_2 = ms_ws_r_exc_type[0] | io_csr_exc_intr_t; // @[Wb_stage.scala 29:41]
  wire [31:0] _io_exc_br_exc_target_T_8 = ms_ws_r_pc + 32'h4; // @[Wb_stage.scala 31:79]
  wire [31:0] _io_exc_br_exc_target_T_9 = ms_ws_r_exc_type[2] ? _io_exc_br_exc_target_T_8 : 32'h0; // @[Mux.scala 101:16]
  wire [31:0] _io_exc_br_exc_target_T_10 = ms_ws_r_exc_type[1] ? io_csr_exc_mret_addr : _io_exc_br_exc_target_T_9; // @[Mux.scala 101:16]
  wire [2:0] _GEN_22 = {{2'd0}, ms_ws_r_exc_type[0]}; // @[Mux.scala 81:61]
  assign io_mem2wb_ready = 1'h1; // @[Wb_stage.scala 18:21]
  assign io_wb2rf_rf_we = ms_ws_r_gr_we & _ws_valid_T & ws_valid; // @[Wb_stage.scala 48:50]
  assign io_wb2rf_waddr = ms_ws_r_dest; // @[Wb_stage.scala 49:20]
  assign io_wb2rf_wdata = |ms_ws_r_csr_op ? io_csr_op_csr_old : ms_ws_r_result; // @[Wb_stage.scala 50:26]
  assign io_exc_br_exc_br = |ms_ws_r_exc_type & ws_valid | io_csr_exc_intr_t; // @[Wb_stage.scala 17:67]
  assign io_exc_br_exc_target = _io_exc_br_exc_target_T_2 ? io_csr_out_mtvec : _io_exc_br_exc_target_T_10; // @[Mux.scala 101:16]
  assign io_csr_op_csr_en = ws_valid; // @[Wb_stage.scala 38:26]
  assign io_csr_op_csr_op = ms_ws_r_csr_op; // @[Wb_stage.scala 39:26]
  assign io_csr_op_csr_num = ms_ws_r_csr_num; // @[Wb_stage.scala 40:26]
  assign io_csr_op_csr_wdata = ms_ws_r_rs1; // @[Wb_stage.scala 41:26]
  assign io_csr_exc_ecall = ms_ws_r_exc_type[0] & ws_valid; // @[Wb_stage.scala 43:59]
  assign io_csr_exc_mret = ms_ws_r_exc_type[1] & ws_valid; // @[Wb_stage.scala 44:59]
  assign io_csr_exc_epc = ms_ws_r_pc[31:2]; // @[Wb_stage.scala 45:39]
  assign io_csr_exc_exc_code = _GEN_22 == ms_ws_r_exc_type ? 64'hb : 64'h0; // @[Mux.scala 81:58]
  assign io_ws_forward_valid = ws_valid; // @[Wb_stage.scala 52:29]
  assign io_ws_forward_bits_en = ws_valid & ms_ws_r_gr_we; // @[Wb_stage.scala 53:41]
  assign io_ws_forward_bits_dest = io_wb2rf_waddr; // @[Wb_stage.scala 54:29]
  assign io_ws_forward_bits_data = io_wb2rf_wdata; // @[Wb_stage.scala 55:29]
  always @(posedge clock) begin
    if (reset) begin // @[Wb_stage.scala 15:31]
      ws_valid <= 1'h0; // @[Wb_stage.scala 15:31]
    end else begin
      ws_valid <= ~has_trap & io_mem2wb_valid; // @[Wb_stage.scala 19:21]
    end
    if (reset) begin // @[Wb_stage.scala 16:31]
      ms_ws_r_pc <= 32'h0; // @[Wb_stage.scala 16:31]
    end else if (has_trap) begin // @[Wb_stage.scala 20:19]
      ms_ws_r_pc <= io_exc_br_exc_target; // @[Wb_stage.scala 21:20]
    end else if (_T) begin // @[Wb_stage.scala 22:32]
      ms_ws_r_pc <= io_mem2wb_bits_pc; // @[Wb_stage.scala 23:21]
    end
    if (reset) begin // @[Wb_stage.scala 16:31]
      ms_ws_r_gr_we <= 1'h0; // @[Wb_stage.scala 16:31]
    end else if (!(has_trap)) begin // @[Wb_stage.scala 20:19]
      if (_T) begin // @[Wb_stage.scala 22:32]
        ms_ws_r_gr_we <= io_mem2wb_bits_gr_we; // @[Wb_stage.scala 23:21]
      end
    end
    if (reset) begin // @[Wb_stage.scala 16:31]
      ms_ws_r_csr_op <= 3'h0; // @[Wb_stage.scala 16:31]
    end else if (!(has_trap)) begin // @[Wb_stage.scala 20:19]
      if (_T) begin // @[Wb_stage.scala 22:32]
        ms_ws_r_csr_op <= io_mem2wb_bits_csr_op; // @[Wb_stage.scala 23:21]
      end
    end
    if (reset) begin // @[Wb_stage.scala 16:31]
      ms_ws_r_exc_type <= 3'h0; // @[Wb_stage.scala 16:31]
    end else if (!(has_trap)) begin // @[Wb_stage.scala 20:19]
      if (_T) begin // @[Wb_stage.scala 22:32]
        ms_ws_r_exc_type <= io_mem2wb_bits_exc_type; // @[Wb_stage.scala 23:21]
      end
    end
    if (reset) begin // @[Wb_stage.scala 16:31]
      ms_ws_r_dest <= 5'h0; // @[Wb_stage.scala 16:31]
    end else if (!(has_trap)) begin // @[Wb_stage.scala 20:19]
      if (_T) begin // @[Wb_stage.scala 22:32]
        ms_ws_r_dest <= io_mem2wb_bits_dest; // @[Wb_stage.scala 23:21]
      end
    end
    if (reset) begin // @[Wb_stage.scala 16:31]
      ms_ws_r_result <= 64'h0; // @[Wb_stage.scala 16:31]
    end else if (!(has_trap)) begin // @[Wb_stage.scala 20:19]
      if (_T) begin // @[Wb_stage.scala 22:32]
        ms_ws_r_result <= io_mem2wb_bits_result; // @[Wb_stage.scala 23:21]
      end
    end
    if (reset) begin // @[Wb_stage.scala 16:31]
      ms_ws_r_csr_num <= 12'h0; // @[Wb_stage.scala 16:31]
    end else if (!(has_trap)) begin // @[Wb_stage.scala 20:19]
      if (_T) begin // @[Wb_stage.scala 22:32]
        ms_ws_r_csr_num <= io_mem2wb_bits_csr_num; // @[Wb_stage.scala 23:21]
      end
    end
    if (reset) begin // @[Wb_stage.scala 16:31]
      ms_ws_r_rs1 <= 64'h0; // @[Wb_stage.scala 16:31]
    end else if (!(has_trap)) begin // @[Wb_stage.scala 20:19]
      if (_T) begin // @[Wb_stage.scala 22:32]
        ms_ws_r_rs1 <= io_mem2wb_bits_rs1; // @[Wb_stage.scala 23:21]
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ws_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  ms_ws_r_pc = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  ms_ws_r_gr_we = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  ms_ws_r_csr_op = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  ms_ws_r_exc_type = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  ms_ws_r_dest = _RAND_5[4:0];
  _RAND_6 = {2{`RANDOM}};
  ms_ws_r_result = _RAND_6[63:0];
  _RAND_7 = {1{`RANDOM}};
  ms_ws_r_csr_num = _RAND_7[11:0];
  _RAND_8 = {2{`RANDOM}};
  ms_ws_r_rs1 = _RAND_8[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_Csr(
  input         clock,
  input         reset,
  input         io_op_csr_en,
  input  [2:0]  io_op_csr_op,
  input  [11:0] io_op_csr_num,
  input  [63:0] io_op_csr_wdata,
  output [63:0] io_op_csr_old,
  output [31:0] io_out_mtvec,
  input         io_exc_ecall,
  input         io_exc_mret,
  input  [29:0] io_exc_epc,
  input  [63:0] io_exc_exc_code,
  output        io_exc_intr_t,
  output [31:0] io_exc_mret_addr,
  input         io_timer_intr,
  input         io_external_intr,
  input         io_timer_intr_clr
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [63:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
`endif // RANDOMIZE_REG_INIT
  reg [1:0] mstatus_sxl; // @[Csr.scala 67:31]
  reg [1:0] mstatus_uxl; // @[Csr.scala 68:31]
  reg [1:0] mstatus_mpp; // @[Csr.scala 69:31]
  reg  mstatus_mie; // @[Csr.scala 70:31]
  reg  mstatus_mpie; // @[Csr.scala 71:31]
  reg [63:0] mcause; // @[Csr.scala 72:26]
  reg [29:0] mepc; // @[Csr.scala 73:26]
  reg [29:0] mtvec; // @[Csr.scala 74:26]
  reg  mie_meie; // @[Csr.scala 75:27]
  reg  mie_mtie; // @[Csr.scala 76:27]
  reg  mip_meip; // @[Csr.scala 77:27]
  reg  mip_mtip; // @[Csr.scala 78:27]
  wire [63:0] mstatus_rval = {28'h0,mstatus_sxl,mstatus_uxl,19'h0,mstatus_mpp,3'h0,mstatus_mpie,3'h0,mstatus_mie,3'h0}; // @[Cat.scala 33:92]
  wire [31:0] mtvec_rval = {mtvec,2'h0}; // @[Cat.scala 33:92]
  wire [31:0] mepc_rval = {mepc,2'h0}; // @[Cat.scala 33:92]
  wire [63:0] mie_rval = {52'h0,mie_meie,3'h0,mie_mtie,7'h0}; // @[Cat.scala 33:92]
  wire [63:0] mip_rval = {52'h0,mip_meip,3'h0,mip_mtip,7'h0}; // @[Cat.scala 33:92]
  wire  has_t_intr_m = io_timer_intr & mstatus_mie & mie_mtie & ~io_timer_intr_clr; // @[Csr.scala 86:68]
  wire  has_e_intr_m = io_external_intr & mstatus_mie & mie_meie; // @[Csr.scala 87:56]
  wire  has_intr = has_t_intr_m | has_e_intr_m; // @[Csr.scala 88:37]
  wire [5:0] _csr_1H_T_1 = 12'h300 == io_op_csr_num ? 6'h1 : 6'h0; // @[Mux.scala 81:58]
  wire [5:0] _csr_1H_T_3 = 12'h305 == io_op_csr_num ? 6'h2 : _csr_1H_T_1; // @[Mux.scala 81:58]
  wire [5:0] _csr_1H_T_5 = 12'h341 == io_op_csr_num ? 6'h4 : _csr_1H_T_3; // @[Mux.scala 81:58]
  wire [5:0] _csr_1H_T_7 = 12'h342 == io_op_csr_num ? 6'h8 : _csr_1H_T_5; // @[Mux.scala 81:58]
  wire [5:0] _csr_1H_T_9 = 12'h304 == io_op_csr_num ? 6'h10 : _csr_1H_T_7; // @[Mux.scala 81:58]
  wire [5:0] csr_1H = 12'h344 == io_op_csr_num ? 6'h20 : _csr_1H_T_9; // @[Mux.scala 81:58]
  wire  csr_en = |io_op_csr_op & io_op_csr_en; // @[Csr.scala 98:48]
  wire [63:0] _csr_src_T_6 = csr_1H[0] ? mstatus_rval : 64'h0; // @[Mux.scala 27:73]
  wire [31:0] _csr_src_T_7 = csr_1H[1] ? mtvec_rval : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _csr_src_T_8 = csr_1H[2] ? mepc_rval : 32'h0; // @[Mux.scala 27:73]
  wire [63:0] _csr_src_T_9 = csr_1H[3] ? mcause : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _csr_src_T_10 = csr_1H[4] ? mie_rval : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _csr_src_T_11 = csr_1H[5] ? mip_rval : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _GEN_29 = {{32'd0}, _csr_src_T_7}; // @[Mux.scala 27:73]
  wire [63:0] _csr_src_T_12 = _csr_src_T_6 | _GEN_29; // @[Mux.scala 27:73]
  wire [63:0] _GEN_30 = {{32'd0}, _csr_src_T_8}; // @[Mux.scala 27:73]
  wire [63:0] _csr_src_T_13 = _csr_src_T_12 | _GEN_30; // @[Mux.scala 27:73]
  wire [63:0] _csr_src_T_14 = _csr_src_T_13 | _csr_src_T_9; // @[Mux.scala 27:73]
  wire [63:0] _csr_src_T_15 = _csr_src_T_14 | _csr_src_T_10; // @[Mux.scala 27:73]
  wire [63:0] csr_src = _csr_src_T_15 | _csr_src_T_11; // @[Mux.scala 27:73]
  wire [63:0] csrrs_res = csr_src | io_op_csr_wdata; // @[Csr.scala 107:33]
  wire [63:0] _csrrc_res_T = ~io_op_csr_wdata; // @[Csr.scala 108:36]
  wire [63:0] csrrc_res = csr_src & _csrrc_res_T; // @[Csr.scala 108:33]
  wire [63:0] _csr_res_T_3 = io_op_csr_op[0] ? io_op_csr_wdata : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _csr_res_T_4 = io_op_csr_op[1] ? csrrs_res : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _csr_res_T_5 = io_op_csr_op[2] ? csrrc_res : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _csr_res_T_6 = _csr_res_T_3 | _csr_res_T_4; // @[Mux.scala 27:73]
  wire [63:0] csr_res = _csr_res_T_6 | _csr_res_T_5; // @[Mux.scala 27:73]
  wire  _T = io_exc_ecall | has_intr; // @[Csr.scala 117:27]
  wire  _GEN_3 = csr_en & csr_1H[0] ? csr_res[7] : mstatus_mpie; // @[Csr.scala 124:41 128:26 71:31]
  wire  _GEN_6 = io_exc_mret | _GEN_3; // @[Csr.scala 121:33 123:26]
  wire [63:0] _GEN_18 = csr_en & csr_1H[3] ? csr_res : mcause; // @[Csr.scala 148:41 149:21 72:26]
  wire  _T_13 = csr_en & csr_1H[5]; // @[Csr.scala 161:27]
  wire  _GEN_24 = csr_en & csr_1H[5] ? csr_res[7] : mip_mtip; // @[Csr.scala 161:40 162:22 78:27]
  wire  _GEN_25 = io_timer_intr_clr ? 1'h0 : _GEN_24; // @[Csr.scala 159:38 160:22]
  wire  _GEN_26 = has_t_intr_m | _GEN_25; // @[Csr.scala 157:27 158:22]
  wire  _GEN_27 = _T_13 ? csr_res[11] : mip_meip; // @[Csr.scala 166:40 167:22 77:27]
  wire  _GEN_28 = has_e_intr_m | _GEN_27; // @[Csr.scala 164:27 165:22]
  assign io_op_csr_old = _csr_src_T_15 | _csr_src_T_11; // @[Mux.scala 27:73]
  assign io_out_mtvec = {mtvec,2'h0}; // @[Cat.scala 33:92]
  assign io_exc_intr_t = has_t_intr_m | has_e_intr_m; // @[Csr.scala 88:37]
  assign io_exc_mret_addr = {mepc,2'h0}; // @[Cat.scala 33:92]
  always @(posedge clock) begin
    if (reset) begin // @[Csr.scala 67:31]
      mstatus_sxl <= 2'h2; // @[Csr.scala 67:31]
    end else if (!(io_exc_ecall | has_intr)) begin // @[Csr.scala 117:39]
      if (!(io_exc_mret)) begin // @[Csr.scala 121:33]
        if (csr_en & csr_1H[0]) begin // @[Csr.scala 124:41]
          mstatus_sxl <= csr_res[35:34]; // @[Csr.scala 125:26]
        end
      end
    end
    if (reset) begin // @[Csr.scala 68:31]
      mstatus_uxl <= 2'h2; // @[Csr.scala 68:31]
    end else if (!(io_exc_ecall | has_intr)) begin // @[Csr.scala 117:39]
      if (!(io_exc_mret)) begin // @[Csr.scala 121:33]
        if (csr_en & csr_1H[0]) begin // @[Csr.scala 124:41]
          mstatus_uxl <= csr_res[33:32]; // @[Csr.scala 126:26]
        end
      end
    end
    if (reset) begin // @[Csr.scala 69:31]
      mstatus_mpp <= 2'h3; // @[Csr.scala 69:31]
    end else if (io_exc_ecall | has_intr) begin // @[Csr.scala 117:39]
      mstatus_mpp <= 2'h3; // @[Csr.scala 120:26]
    end else if (!(io_exc_mret)) begin // @[Csr.scala 121:33]
      if (csr_en & csr_1H[0]) begin // @[Csr.scala 124:41]
        mstatus_mpp <= csr_res[12:11]; // @[Csr.scala 127:26]
      end
    end
    if (reset) begin // @[Csr.scala 70:31]
      mstatus_mie <= 1'h0; // @[Csr.scala 70:31]
    end else if (io_exc_ecall | has_intr) begin // @[Csr.scala 117:39]
      mstatus_mie <= 1'h0; // @[Csr.scala 118:26]
    end else if (io_exc_mret) begin // @[Csr.scala 121:33]
      mstatus_mie <= mstatus_mpie; // @[Csr.scala 122:26]
    end else if (csr_en & csr_1H[0]) begin // @[Csr.scala 124:41]
      mstatus_mie <= csr_res[3]; // @[Csr.scala 129:26]
    end
    if (reset) begin // @[Csr.scala 71:31]
      mstatus_mpie <= 1'h0; // @[Csr.scala 71:31]
    end else if (io_exc_ecall | has_intr) begin // @[Csr.scala 117:39]
      mstatus_mpie <= mstatus_mie; // @[Csr.scala 119:26]
    end else begin
      mstatus_mpie <= _GEN_6;
    end
    if (reset) begin // @[Csr.scala 72:26]
      mcause <= 64'h0; // @[Csr.scala 72:26]
    end else if (io_exc_ecall) begin // @[Csr.scala 142:27]
      mcause <= io_exc_exc_code; // @[Csr.scala 143:21]
    end else if (has_t_intr_m) begin // @[Csr.scala 144:34]
      mcause <= 64'h8000000000000007; // @[Csr.scala 145:21]
    end else if (has_e_intr_m) begin // @[Csr.scala 146:34]
      mcause <= 64'h800000000000000b; // @[Csr.scala 147:21]
    end else begin
      mcause <= _GEN_18;
    end
    if (reset) begin // @[Csr.scala 73:26]
      mepc <= 30'h0; // @[Csr.scala 73:26]
    end else if (_T) begin // @[Csr.scala 136:39]
      mepc <= io_exc_epc; // @[Csr.scala 137:21]
    end else if (csr_en & csr_1H[2]) begin // @[Csr.scala 138:41]
      mepc <= csr_res[31:2]; // @[Csr.scala 139:21]
    end
    if (reset) begin // @[Csr.scala 74:26]
      mtvec <= 30'h0; // @[Csr.scala 74:26]
    end else if (csr_en & csr_1H[1]) begin // @[Csr.scala 132:34]
      mtvec <= csr_res[31:2]; // @[Csr.scala 133:21]
    end
    if (reset) begin // @[Csr.scala 75:27]
      mie_meie <= 1'h0; // @[Csr.scala 75:27]
    end else if (csr_en & csr_1H[4]) begin // @[Csr.scala 152:34]
      mie_meie <= csr_res[11]; // @[Csr.scala 153:22]
    end
    if (reset) begin // @[Csr.scala 76:27]
      mie_mtie <= 1'h0; // @[Csr.scala 76:27]
    end else if (csr_en & csr_1H[4]) begin // @[Csr.scala 152:34]
      mie_mtie <= csr_res[7]; // @[Csr.scala 154:22]
    end
    if (reset) begin // @[Csr.scala 77:27]
      mip_meip <= 1'h0; // @[Csr.scala 77:27]
    end else begin
      mip_meip <= _GEN_28;
    end
    if (reset) begin // @[Csr.scala 78:27]
      mip_mtip <= 1'h0; // @[Csr.scala 78:27]
    end else begin
      mip_mtip <= _GEN_26;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  mstatus_sxl = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  mstatus_uxl = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  mstatus_mpp = _RAND_2[1:0];
  _RAND_3 = {1{`RANDOM}};
  mstatus_mie = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  mstatus_mpie = _RAND_4[0:0];
  _RAND_5 = {2{`RANDOM}};
  mcause = _RAND_5[63:0];
  _RAND_6 = {1{`RANDOM}};
  mepc = _RAND_6[29:0];
  _RAND_7 = {1{`RANDOM}};
  mtvec = _RAND_7[29:0];
  _RAND_8 = {1{`RANDOM}};
  mie_meie = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  mie_mtie = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  mip_meip = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  mip_mtip = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_AXIBridge(
  input          clock,
  input          reset,
  output         io_in_req_ready,
  input          io_in_req_valid,
  input          io_in_req_bits_wr,
  input  [31:0]  io_in_req_bits_addr,
  input  [1:0]   io_in_req_bits_size,
  input  [127:0] io_in_req_bits_wdata,
  input  [7:0]   io_in_req_bits_wstrb,
  input          io_in_req_bits_mthrough,
  output [63:0]  io_in_ret_rdata,
  output         io_in_ret_valid,
  output         io_in_rlast,
  input          io_out_ar_ready,
  output         io_out_ar_valid,
  output [31:0]  io_out_ar_bits_araddr,
  output [7:0]   io_out_ar_bits_arlen,
  output [2:0]   io_out_ar_bits_arsize,
  output         io_out_rd_ready,
  input          io_out_rd_valid,
  input  [63:0]  io_out_rd_bits_rdata,
  input          io_out_rd_bits_rlast,
  input          io_out_aw_ready,
  output         io_out_aw_valid,
  output [31:0]  io_out_aw_bits_awaddr,
  output [7:0]   io_out_aw_bits_awlen,
  output [2:0]   io_out_aw_bits_awsize,
  input          io_out_wt_ready,
  output         io_out_wt_valid,
  output [63:0]  io_out_wt_bits_wdata,
  output [7:0]   io_out_wt_bits_wstrb,
  output         io_out_wt_bits_wlast,
  output         io_out_b_ready,
  input          io_out_b_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [127:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  reg [3:0] state; // @[AXIBridge.scala 22:24]
  wire  _state_T_1 = io_out_ar_ready & io_out_ar_valid; // @[Decoupled.scala 52:35]
  wire  _state_T_2 = io_out_aw_ready & io_out_aw_valid; // @[Decoupled.scala 52:35]
  wire [2:0] _state_T_3 = _state_T_2 ? 3'h4 : 3'h1; // @[AXIBridge.scala 24:74]
  wire [2:0] _state_T_4 = _state_T_1 ? 3'h2 : _state_T_3; // @[AXIBridge.scala 24:38]
  wire  _state_T_6 = io_out_rd_ready & io_out_rd_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _state_T_9 = _state_T_6 & io_out_rd_bits_rlast ? 2'h1 : 2'h2; // @[AXIBridge.scala 25:38]
  wire  _state_T_11 = io_out_wt_ready & io_out_wt_valid; // @[Decoupled.scala 52:35]
  wire [3:0] _state_T_14 = _state_T_11 & io_out_wt_bits_wlast ? 4'h8 : 4'h4; // @[AXIBridge.scala 26:38]
  wire  _state_T_16 = io_out_b_ready & io_out_b_valid; // @[Decoupled.scala 52:35]
  wire [3:0] _state_T_17 = _state_T_16 ? 4'h1 : 4'h8; // @[AXIBridge.scala 27:38]
  wire [2:0] _state_T_18 = state[0] ? _state_T_4 : 3'h0; // @[Mux.scala 27:73]
  wire [1:0] _state_T_19 = state[1] ? _state_T_9 : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] _state_T_20 = state[2] ? _state_T_14 : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _state_T_21 = state[3] ? _state_T_17 : 4'h0; // @[Mux.scala 27:73]
  wire [2:0] _GEN_14 = {{1'd0}, _state_T_19}; // @[Mux.scala 27:73]
  wire [2:0] _state_T_22 = _state_T_18 | _GEN_14; // @[Mux.scala 27:73]
  wire [3:0] _GEN_15 = {{1'd0}, _state_T_22}; // @[Mux.scala 27:73]
  wire [3:0] _state_T_23 = _GEN_15 | _state_T_20; // @[Mux.scala 27:73]
  wire [3:0] _state_T_24 = _state_T_23 | _state_T_21; // @[Mux.scala 27:73]
  reg  rd_widx; // @[AXIBridge.scala 29:38]
  reg  rd_after_wt_r; // @[AXIBridge.scala 30:38]
  reg [127:0] wdata_r; // @[AXIBridge.scala 31:38]
  reg [27:0] wtag_r; // @[AXIBridge.scala 32:38]
  reg [7:0] wstrb_r; // @[AXIBridge.scala 33:38]
  reg  wt_widx; // @[AXIBridge.scala 34:38]
  wire  init_widx = io_in_req_bits_addr[3]; // @[AXIBridge.scala 35:50]
  reg  burst_cnt; // @[AXIBridge.scala 36:38]
  reg [7:0] burst_len; // @[AXIBridge.scala 37:38]
  wire  _rd_after_wt_T_3 = io_in_req_valid & ~io_in_req_bits_wr & state[0]; // @[AXIBridge.scala 39:78]
  wire  _rd_after_wt_T_4 = ~io_in_req_bits_mthrough; // @[AXIBridge.scala 40:54]
  wire  _rd_after_wt_T_5 = io_in_req_valid & ~io_in_req_bits_wr & state[0] & _rd_after_wt_T_4; // @[AXIBridge.scala 39:90]
  wire  _rd_after_wt_T_7 = wtag_r == io_in_req_bits_addr[31:4]; // @[AXIBridge.scala 41:37]
  wire  rd_after_wt = _rd_after_wt_T_5 & _rd_after_wt_T_7; // @[AXIBridge.scala 40:63]
  wire [63:0] rd_after_wt_rdata = rd_widx ? wdata_r[127:64] : wdata_r[63:0]; // @[Mux.scala 81:58]
  wire  _GEN_0 = io_in_rlast & io_in_ret_valid ? 1'h0 : rd_after_wt_r; // @[AXIBridge.scala 48:49 49:23 30:38]
  wire  _GEN_2 = rd_after_wt | _GEN_0; // @[AXIBridge.scala 45:23 47:23]
  wire [2:0] _io_out_ar_bits_araddr_T_3 = io_in_req_bits_mthrough ? io_in_req_bits_addr[2:0] : 3'h0; // @[AXIBridge.scala 52:66]
  wire [2:0] _io_out_ar_bits_arsize_T_1 = {1'h0,io_in_req_bits_size}; // @[Cat.scala 33:92]
  wire  _T_2 = io_in_req_valid & io_in_req_bits_wr; // @[AXIBridge.scala 61:26]
  assign io_in_req_ready = _state_T_1 | _state_T_11 | rd_after_wt; // @[AXIBridge.scala 87:62]
  assign io_in_ret_rdata = rd_after_wt_r ? rd_after_wt_rdata : io_out_rd_bits_rdata; // @[AXIBridge.scala 58:34]
  assign io_in_ret_valid = _state_T_6 | _state_T_16 | rd_after_wt_r; // @[AXIBridge.scala 88:62]
  assign io_in_rlast = rd_after_wt_r | io_out_rd_bits_rlast; // @[AXIBridge.scala 59:34]
  assign io_out_ar_valid = _rd_after_wt_T_3 & ~rd_after_wt; // @[AXIBridge.scala 51:90]
  assign io_out_ar_bits_araddr = {io_in_req_bits_addr[31:3],_io_out_ar_bits_araddr_T_3}; // @[Cat.scala 33:92]
  assign io_out_ar_bits_arlen = io_in_req_bits_mthrough ? 8'h0 : 8'h1; // @[AXIBridge.scala 54:34]
  assign io_out_ar_bits_arsize = io_in_req_bits_mthrough ? _io_out_ar_bits_arsize_T_1 : 3'h3; // @[AXIBridge.scala 55:34]
  assign io_out_rd_ready = state[1]; // @[AXIBridge.scala 57:36]
  assign io_out_aw_valid = _T_2 & state[0]; // @[AXIBridge.scala 75:78]
  assign io_out_aw_bits_awaddr = {io_in_req_bits_addr[31:3],_io_out_ar_bits_araddr_T_3}; // @[Cat.scala 33:92]
  assign io_out_aw_bits_awlen = io_in_req_bits_mthrough ? 8'h0 : 8'h1; // @[AXIBridge.scala 78:34]
  assign io_out_aw_bits_awsize = io_in_req_bits_mthrough ? _io_out_ar_bits_arsize_T_1 : 3'h3; // @[AXIBridge.scala 79:34]
  assign io_out_wt_valid = state[2]; // @[AXIBridge.scala 81:36]
  assign io_out_wt_bits_wdata = wt_widx ? wdata_r[127:64] : wdata_r[63:0]; // @[Mux.scala 81:58]
  assign io_out_wt_bits_wstrb = wstrb_r; // @[AXIBridge.scala 83:28]
  assign io_out_wt_bits_wlast = burst_cnt == burst_len[0] & state[2]; // @[AXIBridge.scala 84:88]
  assign io_out_b_ready = state[3]; // @[AXIBridge.scala 85:36]
  always @(posedge clock) begin
    if (reset) begin // @[AXIBridge.scala 22:24]
      state <= 4'h1; // @[AXIBridge.scala 22:24]
    end else begin
      state <= _state_T_24; // @[AXIBridge.scala 23:11]
    end
    if (reset) begin // @[AXIBridge.scala 29:38]
      rd_widx <= 1'h0; // @[AXIBridge.scala 29:38]
    end else if (rd_after_wt) begin // @[AXIBridge.scala 45:23]
      rd_widx <= init_widx; // @[AXIBridge.scala 46:23]
    end
    if (reset) begin // @[AXIBridge.scala 30:38]
      rd_after_wt_r <= 1'h0; // @[AXIBridge.scala 30:38]
    end else begin
      rd_after_wt_r <= _GEN_2;
    end
    if (reset) begin // @[AXIBridge.scala 31:38]
      wdata_r <= 128'h0; // @[AXIBridge.scala 31:38]
    end else if (io_in_req_valid & io_in_req_bits_wr & _state_T_2) begin // @[AXIBridge.scala 61:76]
      wdata_r <= io_in_req_bits_wdata; // @[AXIBridge.scala 62:19]
    end
    if (reset) begin // @[AXIBridge.scala 32:38]
      wtag_r <= 28'h0; // @[AXIBridge.scala 32:38]
    end else if (io_in_req_valid & io_in_req_bits_wr & _state_T_2) begin // @[AXIBridge.scala 61:76]
      wtag_r <= io_in_req_bits_addr[31:4]; // @[AXIBridge.scala 63:19]
    end else if (!(_state_T_11)) begin // @[AXIBridge.scala 68:33]
      if (_state_T_16) begin // @[AXIBridge.scala 71:31]
        wtag_r <= 28'h0; // @[AXIBridge.scala 72:19]
      end
    end
    if (reset) begin // @[AXIBridge.scala 33:38]
      wstrb_r <= 8'h0; // @[AXIBridge.scala 33:38]
    end else if (io_in_req_valid & io_in_req_bits_wr & _state_T_2) begin // @[AXIBridge.scala 61:76]
      wstrb_r <= io_in_req_bits_wstrb; // @[AXIBridge.scala 64:19]
    end
    if (reset) begin // @[AXIBridge.scala 34:38]
      wt_widx <= 1'h0; // @[AXIBridge.scala 34:38]
    end else if (io_in_req_valid & io_in_req_bits_wr & _state_T_2) begin // @[AXIBridge.scala 61:76]
      wt_widx <= init_widx; // @[AXIBridge.scala 65:19]
    end else if (_state_T_11) begin // @[AXIBridge.scala 68:33]
      wt_widx <= wt_widx + 1'h1; // @[AXIBridge.scala 70:19]
    end
    if (reset) begin // @[AXIBridge.scala 36:38]
      burst_cnt <= 1'h0; // @[AXIBridge.scala 36:38]
    end else if (io_in_req_valid & io_in_req_bits_wr & _state_T_2) begin // @[AXIBridge.scala 61:76]
      burst_cnt <= 1'h0; // @[AXIBridge.scala 67:19]
    end else if (_state_T_11) begin // @[AXIBridge.scala 68:33]
      burst_cnt <= burst_cnt + 1'h1; // @[AXIBridge.scala 69:19]
    end else if (_state_T_16) begin // @[AXIBridge.scala 71:31]
      burst_cnt <= 1'h0; // @[AXIBridge.scala 73:19]
    end
    if (reset) begin // @[AXIBridge.scala 37:38]
      burst_len <= 8'h0; // @[AXIBridge.scala 37:38]
    end else if (io_in_req_valid & io_in_req_bits_wr & _state_T_2) begin // @[AXIBridge.scala 61:76]
      burst_len <= io_out_aw_bits_awlen; // @[AXIBridge.scala 66:19]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  state = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  rd_widx = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rd_after_wt_r = _RAND_2[0:0];
  _RAND_3 = {4{`RANDOM}};
  wdata_r = _RAND_3[127:0];
  _RAND_4 = {1{`RANDOM}};
  wtag_r = _RAND_4[27:0];
  _RAND_5 = {1{`RANDOM}};
  wstrb_r = _RAND_5[7:0];
  _RAND_6 = {1{`RANDOM}};
  wt_widx = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  burst_cnt = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  burst_len = _RAND_8[7:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_MemoryController(
  output         io_in_req_ready,
  input          io_in_req_valid,
  input          io_in_req_bits_wr,
  input  [31:0]  io_in_req_bits_addr,
  input  [1:0]   io_in_req_bits_size,
  input  [127:0] io_in_req_bits_wdata,
  input  [7:0]   io_in_req_bits_wstrb,
  input          io_in_req_bits_mthrough,
  output [63:0]  io_in_ret_rdata,
  output         io_in_ret_valid,
  output         io_in_rlast,
  output         io_clint_out_en,
  output         io_clint_out_wr,
  output [31:0]  io_clint_out_addr,
  output [63:0]  io_clint_out_wdata,
  input          io_clint_out_clint_hit,
  input          io_clint_out_ret_valid,
  input  [63:0]  io_clint_out_rdata,
  input          io_axi_out_req_ready,
  output         io_axi_out_req_valid,
  output         io_axi_out_req_bits_wr,
  output [31:0]  io_axi_out_req_bits_addr,
  output [1:0]   io_axi_out_req_bits_size,
  output [127:0] io_axi_out_req_bits_wdata,
  output [7:0]   io_axi_out_req_bits_wstrb,
  output         io_axi_out_req_bits_mthrough,
  input  [63:0]  io_axi_out_ret_rdata,
  input          io_axi_out_ret_valid,
  input          io_axi_out_rlast
);
  wire  io_widx = io_in_req_bits_addr[3]; // @[MM.scala 20:46]
  assign io_in_req_ready = io_clint_out_clint_hit | io_axi_out_req_ready; // @[MM.scala 31:32]
  assign io_in_ret_rdata = io_clint_out_ret_valid ? io_clint_out_rdata : io_axi_out_ret_rdata; // @[MM.scala 33:32]
  assign io_in_ret_valid = io_clint_out_ret_valid | io_axi_out_ret_valid; // @[MM.scala 32:32]
  assign io_in_rlast = io_clint_out_ret_valid | io_axi_out_rlast; // @[MM.scala 34:32]
  assign io_clint_out_en = io_in_req_valid & io_clint_out_clint_hit; // @[MM.scala 23:43]
  assign io_clint_out_wr = io_in_req_bits_wr; // @[MM.scala 24:24]
  assign io_clint_out_addr = io_in_req_bits_addr; // @[MM.scala 25:24]
  assign io_clint_out_wdata = io_widx ? io_in_req_bits_wdata[127:64] : io_in_req_bits_wdata[63:0]; // @[Mux.scala 81:58]
  assign io_axi_out_req_valid = io_in_req_valid & ~io_clint_out_clint_hit; // @[MM.scala 29:46]
  assign io_axi_out_req_bits_wr = io_in_req_bits_wr; // @[MM.scala 28:26]
  assign io_axi_out_req_bits_addr = io_in_req_bits_addr; // @[MM.scala 28:26]
  assign io_axi_out_req_bits_size = io_in_req_bits_size; // @[MM.scala 28:26]
  assign io_axi_out_req_bits_wdata = io_in_req_bits_wdata; // @[MM.scala 28:26]
  assign io_axi_out_req_bits_wstrb = io_in_req_bits_wstrb; // @[MM.scala 28:26]
  assign io_axi_out_req_bits_mthrough = io_in_req_bits_mthrough; // @[MM.scala 28:26]
endmodule
module ysyx_22051110_CacheStage1(
  output        io_cpu_ready,
  input         io_cpu_valid,
  input         io_cpu_bits_wr,
  input  [31:0] io_cpu_bits_addr,
  input  [1:0]  io_cpu_bits_size,
  input  [63:0] io_cpu_bits_wdata,
  input  [7:0]  io_cpu_bits_wstrb,
  input         io_cpu_bits_mthrough,
  input         io_cpu_bits_fencei,
  output        io_rd_en,
  output [4:0]  io_rd_index,
  input         io_s1_to_s2_ready,
  output        io_s1_to_s2_valid,
  output        io_s1_to_s2_bits_wr,
  output [63:0] io_s1_to_s2_bits_wdata,
  output [7:0]  io_s1_to_s2_bits_wstrb,
  output        io_s1_to_s2_bits_mthrough,
  output [22:0] io_s1_to_s2_bits_tag,
  output [4:0]  io_s1_to_s2_bits_index,
  output [3:0]  io_s1_to_s2_bits_offset,
  output [1:0]  io_s1_to_s2_bits_size,
  output        io_s1_to_s2_bits_fencei
);
  assign io_cpu_ready = io_s1_to_s2_ready & io_s1_to_s2_valid; // @[Decoupled.scala 52:35]
  assign io_rd_en = io_s1_to_s2_ready & io_s1_to_s2_valid; // @[Decoupled.scala 52:35]
  assign io_rd_index = io_cpu_bits_addr[8:4]; // @[CacheCore.scala 19:36]
  assign io_s1_to_s2_valid = io_cpu_valid; // @[CacheCore.scala 23:31]
  assign io_s1_to_s2_bits_wr = io_cpu_bits_wr; // @[CacheCore.scala 24:31]
  assign io_s1_to_s2_bits_wdata = io_cpu_bits_wdata; // @[CacheCore.scala 25:31]
  assign io_s1_to_s2_bits_wstrb = io_cpu_bits_wstrb; // @[CacheCore.scala 26:31]
  assign io_s1_to_s2_bits_mthrough = io_cpu_bits_mthrough; // @[CacheCore.scala 27:31]
  assign io_s1_to_s2_bits_tag = io_cpu_bits_addr[31:9]; // @[CacheCore.scala 18:36]
  assign io_s1_to_s2_bits_index = io_cpu_bits_addr[8:4]; // @[CacheCore.scala 19:36]
  assign io_s1_to_s2_bits_offset = io_cpu_bits_addr[3:0]; // @[CacheCore.scala 20:36]
  assign io_s1_to_s2_bits_size = io_cpu_bits_size; // @[CacheCore.scala 29:31]
  assign io_s1_to_s2_bits_fencei = io_cpu_bits_fencei; // @[CacheCore.scala 28:31]
endmodule
module ysyx_22051110_CacheStage2(
  input         clock,
  input         reset,
  output        io_s1_to_s2_ready,
  input         io_s1_to_s2_valid,
  input         io_s1_to_s2_bits_wr,
  input  [63:0] io_s1_to_s2_bits_wdata,
  input  [7:0]  io_s1_to_s2_bits_wstrb,
  input         io_s1_to_s2_bits_mthrough,
  input  [22:0] io_s1_to_s2_bits_tag,
  input  [4:0]  io_s1_to_s2_bits_index,
  input  [3:0]  io_s1_to_s2_bits_offset,
  input  [1:0]  io_s1_to_s2_bits_size,
  input         io_s1_to_s2_bits_fencei,
  input         io_rd_lines_0_valid,
  input         io_rd_lines_0_dirty,
  input  [22:0] io_rd_lines_0_tag,
  input  [63:0] io_rd_lines_0_data_0,
  input  [63:0] io_rd_lines_0_data_1,
  input         io_rd_lines_1_valid,
  input         io_rd_lines_1_dirty,
  input  [22:0] io_rd_lines_1_tag,
  input  [63:0] io_rd_lines_1_data_0,
  input  [63:0] io_rd_lines_1_data_1,
  input         io_rd_lines_2_valid,
  input         io_rd_lines_2_dirty,
  input  [22:0] io_rd_lines_2_tag,
  input  [63:0] io_rd_lines_2_data_0,
  input  [63:0] io_rd_lines_2_data_1,
  input         io_rd_lines_3_valid,
  input         io_rd_lines_3_dirty,
  input  [22:0] io_rd_lines_3_tag,
  input  [63:0] io_rd_lines_3_data_0,
  input  [63:0] io_rd_lines_3_data_1,
  input         io_s2_to_s3_ready,
  output        io_s2_to_s3_valid,
  output        io_s2_to_s3_bits_wr,
  output [63:0] io_s2_to_s3_bits_wdata,
  output [7:0]  io_s2_to_s3_bits_wstrb,
  output        io_s2_to_s3_bits_mthrough,
  output [22:0] io_s2_to_s3_bits_tag,
  output [4:0]  io_s2_to_s3_bits_index,
  output [3:0]  io_s2_to_s3_bits_offset,
  output [1:0]  io_s2_to_s3_bits_size,
  output        io_s2_to_s3_bits_hit,
  output [1:0]  io_s2_to_s3_bits_target_way,
  output        io_s2_to_s3_bits_target_line_valid,
  output        io_s2_to_s3_bits_target_line_dirty,
  output [22:0] io_s2_to_s3_bits_target_line_tag,
  output [63:0] io_s2_to_s3_bits_target_line_data_0,
  output [63:0] io_s2_to_s3_bits_target_line_data_1,
  output        io_s2_to_s3_bits_fencei
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [63:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg  s2_valid; // @[CacheCore.scala 57:37]
  reg  buf_wr; // @[CacheCore.scala 63:29]
  reg [63:0] buf_wdata; // @[CacheCore.scala 63:29]
  reg [7:0] buf_wstrb; // @[CacheCore.scala 63:29]
  reg  buf_mthrough; // @[CacheCore.scala 63:29]
  reg [22:0] buf_tag; // @[CacheCore.scala 63:29]
  reg [4:0] buf_index; // @[CacheCore.scala 63:29]
  reg [3:0] buf_offset; // @[CacheCore.scala 63:29]
  reg [1:0] buf_size; // @[CacheCore.scala 63:29]
  reg  buf_fencei; // @[CacheCore.scala 63:29]
  wire  _T = io_s1_to_s2_ready & io_s1_to_s2_valid; // @[Decoupled.scala 52:35]
  wire  hit1H_0 = buf_tag == io_rd_lines_0_tag & io_rd_lines_0_valid; // @[CacheCore.scala 70:54]
  wire  hit1H_1 = buf_tag == io_rd_lines_1_tag & io_rd_lines_1_valid; // @[CacheCore.scala 70:54]
  wire  hit1H_2 = buf_tag == io_rd_lines_2_tag & io_rd_lines_2_valid; // @[CacheCore.scala 70:54]
  wire  hit1H_3 = buf_tag == io_rd_lines_3_tag & io_rd_lines_3_valid; // @[CacheCore.scala 70:54]
  wire [3:0] _hit_array_T = {hit1H_0,hit1H_1,hit1H_2,hit1H_3}; // @[Cat.scala 33:92]
  wire [3:0] hit_array = {_hit_array_T[0],_hit_array_T[1],_hit_array_T[2],_hit_array_T[3]}; // @[Cat.scala 33:92]
  wire  hit = |hit_array; // @[CacheCore.scala 73:25]
  reg [3:0] replace1H; // @[CacheCore.scala 75:28]
  wire [3:0] _replace1H_T_2 = {replace1H[2:0],replace1H[3]}; // @[Cat.scala 33:92]
  wire [3:0] target_way1H = hit ? hit_array : replace1H; // @[CacheCore.scala 78:27]
  wire [1:0] io_s2_to_s3_bits_target_way_hi = target_way1H[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] io_s2_to_s3_bits_target_way_lo = target_way1H[1:0]; // @[OneHot.scala 31:18]
  wire  _io_s2_to_s3_bits_target_way_T = |io_s2_to_s3_bits_target_way_hi; // @[OneHot.scala 32:14]
  wire [1:0] _io_s2_to_s3_bits_target_way_T_1 = io_s2_to_s3_bits_target_way_hi | io_s2_to_s3_bits_target_way_lo; // @[OneHot.scala 32:28]
  wire [63:0] _io_s2_to_s3_bits_target_line_T_4 = target_way1H[0] ? io_rd_lines_0_data_0 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_s2_to_s3_bits_target_line_T_5 = target_way1H[1] ? io_rd_lines_1_data_0 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_s2_to_s3_bits_target_line_T_6 = target_way1H[2] ? io_rd_lines_2_data_0 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_s2_to_s3_bits_target_line_T_7 = target_way1H[3] ? io_rd_lines_3_data_0 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_s2_to_s3_bits_target_line_T_8 = _io_s2_to_s3_bits_target_line_T_4 | _io_s2_to_s3_bits_target_line_T_5; // @[Mux.scala 27:73]
  wire [63:0] _io_s2_to_s3_bits_target_line_T_9 = _io_s2_to_s3_bits_target_line_T_8 | _io_s2_to_s3_bits_target_line_T_6; // @[Mux.scala 27:73]
  wire [63:0] _io_s2_to_s3_bits_target_line_T_11 = target_way1H[0] ? io_rd_lines_0_data_1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_s2_to_s3_bits_target_line_T_12 = target_way1H[1] ? io_rd_lines_1_data_1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_s2_to_s3_bits_target_line_T_13 = target_way1H[2] ? io_rd_lines_2_data_1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_s2_to_s3_bits_target_line_T_14 = target_way1H[3] ? io_rd_lines_3_data_1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_s2_to_s3_bits_target_line_T_15 = _io_s2_to_s3_bits_target_line_T_11 |
    _io_s2_to_s3_bits_target_line_T_12; // @[Mux.scala 27:73]
  wire [63:0] _io_s2_to_s3_bits_target_line_T_16 = _io_s2_to_s3_bits_target_line_T_15 |
    _io_s2_to_s3_bits_target_line_T_13; // @[Mux.scala 27:73]
  wire [22:0] _io_s2_to_s3_bits_target_line_T_18 = target_way1H[0] ? io_rd_lines_0_tag : 23'h0; // @[Mux.scala 27:73]
  wire [22:0] _io_s2_to_s3_bits_target_line_T_19 = target_way1H[1] ? io_rd_lines_1_tag : 23'h0; // @[Mux.scala 27:73]
  wire [22:0] _io_s2_to_s3_bits_target_line_T_20 = target_way1H[2] ? io_rd_lines_2_tag : 23'h0; // @[Mux.scala 27:73]
  wire [22:0] _io_s2_to_s3_bits_target_line_T_21 = target_way1H[3] ? io_rd_lines_3_tag : 23'h0; // @[Mux.scala 27:73]
  wire [22:0] _io_s2_to_s3_bits_target_line_T_22 = _io_s2_to_s3_bits_target_line_T_18 |
    _io_s2_to_s3_bits_target_line_T_19; // @[Mux.scala 27:73]
  wire [22:0] _io_s2_to_s3_bits_target_line_T_23 = _io_s2_to_s3_bits_target_line_T_22 |
    _io_s2_to_s3_bits_target_line_T_20; // @[Mux.scala 27:73]
  assign io_s1_to_s2_ready = io_s2_to_s3_ready; // @[CacheCore.scala 58:39]
  assign io_s2_to_s3_valid = s2_valid; // @[CacheCore.scala 79:36]
  assign io_s2_to_s3_bits_wr = buf_wr; // @[CacheCore.scala 80:35]
  assign io_s2_to_s3_bits_wdata = buf_wdata; // @[CacheCore.scala 81:35]
  assign io_s2_to_s3_bits_wstrb = buf_wstrb; // @[CacheCore.scala 82:35]
  assign io_s2_to_s3_bits_mthrough = buf_mthrough; // @[CacheCore.scala 83:35]
  assign io_s2_to_s3_bits_tag = buf_tag; // @[CacheCore.scala 86:35]
  assign io_s2_to_s3_bits_index = buf_index; // @[CacheCore.scala 85:35]
  assign io_s2_to_s3_bits_offset = buf_offset; // @[CacheCore.scala 87:35]
  assign io_s2_to_s3_bits_size = buf_size; // @[CacheCore.scala 88:35]
  assign io_s2_to_s3_bits_hit = |hit_array; // @[CacheCore.scala 73:25]
  assign io_s2_to_s3_bits_target_way = {_io_s2_to_s3_bits_target_way_T,_io_s2_to_s3_bits_target_way_T_1[1]}; // @[Cat.scala 33:92]
  assign io_s2_to_s3_bits_target_line_valid = target_way1H[0] & io_rd_lines_0_valid | target_way1H[1] &
    io_rd_lines_1_valid | target_way1H[2] & io_rd_lines_2_valid | target_way1H[3] & io_rd_lines_3_valid; // @[Mux.scala 27:73]
  assign io_s2_to_s3_bits_target_line_dirty = target_way1H[0] & io_rd_lines_0_dirty | target_way1H[1] &
    io_rd_lines_1_dirty | target_way1H[2] & io_rd_lines_2_dirty | target_way1H[3] & io_rd_lines_3_dirty; // @[Mux.scala 27:73]
  assign io_s2_to_s3_bits_target_line_tag = _io_s2_to_s3_bits_target_line_T_23 | _io_s2_to_s3_bits_target_line_T_21; // @[Mux.scala 27:73]
  assign io_s2_to_s3_bits_target_line_data_0 = _io_s2_to_s3_bits_target_line_T_9 | _io_s2_to_s3_bits_target_line_T_7; // @[Mux.scala 27:73]
  assign io_s2_to_s3_bits_target_line_data_1 = _io_s2_to_s3_bits_target_line_T_16 | _io_s2_to_s3_bits_target_line_T_14; // @[Mux.scala 27:73]
  assign io_s2_to_s3_bits_fencei = buf_fencei; // @[CacheCore.scala 84:35]
  always @(posedge clock) begin
    if (reset) begin // @[CacheCore.scala 57:37]
      s2_valid <= 1'h0; // @[CacheCore.scala 57:37]
    end else if (io_s1_to_s2_ready) begin // @[CacheCore.scala 59:28]
      s2_valid <= io_s1_to_s2_valid; // @[CacheCore.scala 60:18]
    end
    if (reset) begin // @[CacheCore.scala 63:29]
      buf_wr <= 1'h0; // @[CacheCore.scala 63:29]
    end else if (_T) begin // @[CacheCore.scala 64:27]
      buf_wr <= io_s1_to_s2_bits_wr; // @[CacheCore.scala 65:19]
    end
    if (reset) begin // @[CacheCore.scala 63:29]
      buf_wdata <= 64'h0; // @[CacheCore.scala 63:29]
    end else if (_T) begin // @[CacheCore.scala 64:27]
      buf_wdata <= io_s1_to_s2_bits_wdata; // @[CacheCore.scala 65:19]
    end
    if (reset) begin // @[CacheCore.scala 63:29]
      buf_wstrb <= 8'h0; // @[CacheCore.scala 63:29]
    end else if (_T) begin // @[CacheCore.scala 64:27]
      buf_wstrb <= io_s1_to_s2_bits_wstrb; // @[CacheCore.scala 65:19]
    end
    if (reset) begin // @[CacheCore.scala 63:29]
      buf_mthrough <= 1'h0; // @[CacheCore.scala 63:29]
    end else if (_T) begin // @[CacheCore.scala 64:27]
      buf_mthrough <= io_s1_to_s2_bits_mthrough; // @[CacheCore.scala 65:19]
    end
    if (reset) begin // @[CacheCore.scala 63:29]
      buf_tag <= 23'h0; // @[CacheCore.scala 63:29]
    end else if (_T) begin // @[CacheCore.scala 64:27]
      buf_tag <= io_s1_to_s2_bits_tag; // @[CacheCore.scala 65:19]
    end
    if (reset) begin // @[CacheCore.scala 63:29]
      buf_index <= 5'h0; // @[CacheCore.scala 63:29]
    end else if (_T) begin // @[CacheCore.scala 64:27]
      buf_index <= io_s1_to_s2_bits_index; // @[CacheCore.scala 65:19]
    end
    if (reset) begin // @[CacheCore.scala 63:29]
      buf_offset <= 4'h0; // @[CacheCore.scala 63:29]
    end else if (_T) begin // @[CacheCore.scala 64:27]
      buf_offset <= io_s1_to_s2_bits_offset; // @[CacheCore.scala 65:19]
    end
    if (reset) begin // @[CacheCore.scala 63:29]
      buf_size <= 2'h0; // @[CacheCore.scala 63:29]
    end else if (_T) begin // @[CacheCore.scala 64:27]
      buf_size <= io_s1_to_s2_bits_size; // @[CacheCore.scala 65:19]
    end
    if (reset) begin // @[CacheCore.scala 63:29]
      buf_fencei <= 1'h0; // @[CacheCore.scala 63:29]
    end else if (_T) begin // @[CacheCore.scala 64:27]
      buf_fencei <= io_s1_to_s2_bits_fencei; // @[CacheCore.scala 65:19]
    end
    if (reset) begin // @[CacheCore.scala 75:28]
      replace1H <= 4'h1; // @[CacheCore.scala 75:28]
    end else begin
      replace1H <= _replace1H_T_2; // @[CacheCore.scala 76:15]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  s2_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buf_wr = _RAND_1[0:0];
  _RAND_2 = {2{`RANDOM}};
  buf_wdata = _RAND_2[63:0];
  _RAND_3 = {1{`RANDOM}};
  buf_wstrb = _RAND_3[7:0];
  _RAND_4 = {1{`RANDOM}};
  buf_mthrough = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  buf_tag = _RAND_5[22:0];
  _RAND_6 = {1{`RANDOM}};
  buf_index = _RAND_6[4:0];
  _RAND_7 = {1{`RANDOM}};
  buf_offset = _RAND_7[3:0];
  _RAND_8 = {1{`RANDOM}};
  buf_size = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  buf_fencei = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  replace1H = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_CacheFencei(
  input          clock,
  input          reset,
  output         io_req_ready,
  input          io_req_valid,
  output         io_ret,
  output         io_meta_flush,
  output         io_rd_en,
  output [4:0]   io_rd_index,
  input          io_rd_lines_0_dirty,
  input  [22:0]  io_rd_lines_0_tag,
  input  [63:0]  io_rd_lines_0_data_0,
  input  [63:0]  io_rd_lines_0_data_1,
  input          io_rd_lines_1_dirty,
  input  [22:0]  io_rd_lines_1_tag,
  input  [63:0]  io_rd_lines_1_data_0,
  input  [63:0]  io_rd_lines_1_data_1,
  input          io_rd_lines_2_dirty,
  input  [22:0]  io_rd_lines_2_tag,
  input  [63:0]  io_rd_lines_2_data_0,
  input  [63:0]  io_rd_lines_2_data_1,
  input          io_rd_lines_3_dirty,
  input  [22:0]  io_rd_lines_3_tag,
  input  [63:0]  io_rd_lines_3_data_0,
  input  [63:0]  io_rd_lines_3_data_1,
  input          io_mem_out_req_ready,
  output         io_mem_out_req_valid,
  output [31:0]  io_mem_out_req_bits_addr,
  output [127:0] io_mem_out_req_bits_wdata,
  input          io_mem_out_ret_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [63:0] _RAND_6;
  reg [63:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [63:0] _RAND_10;
  reg [63:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [63:0] _RAND_14;
  reg [63:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [63:0] _RAND_18;
  reg [63:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  reg [5:0] state; // @[CacheCore.scala 325:31]
  reg [5:0] wb_index; // @[CacheCore.scala 329:31]
  reg [2:0] wb_way; // @[CacheCore.scala 330:31]
  reg  wb_flag; // @[CacheCore.scala 335:31]
  reg  buf_rd_lines_0_dirty; // @[CacheCore.scala 336:31]
  reg [22:0] buf_rd_lines_0_tag; // @[CacheCore.scala 336:31]
  reg [63:0] buf_rd_lines_0_data_0; // @[CacheCore.scala 336:31]
  reg [63:0] buf_rd_lines_0_data_1; // @[CacheCore.scala 336:31]
  reg  buf_rd_lines_1_dirty; // @[CacheCore.scala 336:31]
  reg [22:0] buf_rd_lines_1_tag; // @[CacheCore.scala 336:31]
  reg [63:0] buf_rd_lines_1_data_0; // @[CacheCore.scala 336:31]
  reg [63:0] buf_rd_lines_1_data_1; // @[CacheCore.scala 336:31]
  reg  buf_rd_lines_2_dirty; // @[CacheCore.scala 336:31]
  reg [22:0] buf_rd_lines_2_tag; // @[CacheCore.scala 336:31]
  reg [63:0] buf_rd_lines_2_data_0; // @[CacheCore.scala 336:31]
  reg [63:0] buf_rd_lines_2_data_1; // @[CacheCore.scala 336:31]
  reg  buf_rd_lines_3_dirty; // @[CacheCore.scala 336:31]
  reg [22:0] buf_rd_lines_3_tag; // @[CacheCore.scala 336:31]
  reg [63:0] buf_rd_lines_3_data_0; // @[CacheCore.scala 336:31]
  reg [63:0] buf_rd_lines_3_data_1; // @[CacheCore.scala 336:31]
  wire  wb_done = state[2] & wb_index == 6'h20; // @[CacheCore.scala 342:31]
  wire  wb_index_done = state[5] & wb_way == 3'h4; // @[CacheCore.scala 343:31]
  wire [4:0] wb_index_sel = wb_index[4:0]; // @[CacheCore.scala 344:30]
  wire [1:0] wb_way_sel = wb_way[1:0]; // @[CacheCore.scala 345:28]
  wire  _T = io_req_ready & io_req_valid; // @[Decoupled.scala 52:35]
  wire  _wb_ret_done_T_1 = wb_flag ? io_mem_out_ret_valid : 1'h1; // @[CacheCore.scala 384:35]
  wire  wb_ret_done = state[5] & _wb_ret_done_T_1; // @[CacheCore.scala 384:29]
  wire [5:0] _wb_index_T_1 = wb_index + 6'h1; // @[CacheCore.scala 350:30]
  wire [2:0] _wb_way_T_1 = wb_way + 3'h1; // @[CacheCore.scala 356:26]
  wire  _wb_req_done_T_1 = io_mem_out_req_ready & io_mem_out_req_valid; // @[Decoupled.scala 52:35]
  wire  _wb_req_done_T_2 = io_mem_out_req_valid ? _wb_req_done_T_1 : 1'h1; // @[CacheCore.scala 380:35]
  wire  wb_req_done = state[4] & _wb_req_done_T_2; // @[CacheCore.scala 380:29]
  wire  _GEN_25 = 2'h1 == wb_way_sel ? buf_rd_lines_1_dirty : buf_rd_lines_0_dirty; // @[CacheCore.scala 368:{46,46}]
  wire  _GEN_26 = 2'h2 == wb_way_sel ? buf_rd_lines_2_dirty : _GEN_25; // @[CacheCore.scala 368:{46,46}]
  wire  _GEN_27 = 2'h3 == wb_way_sel ? buf_rd_lines_3_dirty : _GEN_26; // @[CacheCore.scala 368:{46,46}]
  wire [22:0] _GEN_29 = 2'h1 == wb_way_sel ? buf_rd_lines_1_tag : buf_rd_lines_0_tag; // @[Cat.scala 33:{92,92}]
  wire [22:0] _GEN_30 = 2'h2 == wb_way_sel ? buf_rd_lines_2_tag : _GEN_29; // @[Cat.scala 33:{92,92}]
  wire [22:0] _GEN_31 = 2'h3 == wb_way_sel ? buf_rd_lines_3_tag : _GEN_30; // @[Cat.scala 33:{92,92}]
  wire [27:0] io_mem_out_req_bits_addr_hi = {_GEN_31,wb_index_sel}; // @[Cat.scala 33:92]
  wire [63:0] _GEN_33 = 2'h1 == wb_way_sel ? buf_rd_lines_1_data_1 : buf_rd_lines_0_data_1; // @[Cat.scala 33:{92,92}]
  wire [63:0] _GEN_34 = 2'h2 == wb_way_sel ? buf_rd_lines_2_data_1 : _GEN_33; // @[Cat.scala 33:{92,92}]
  wire [63:0] _GEN_35 = 2'h3 == wb_way_sel ? buf_rd_lines_3_data_1 : _GEN_34; // @[Cat.scala 33:{92,92}]
  wire [63:0] _GEN_37 = 2'h1 == wb_way_sel ? buf_rd_lines_1_data_0 : buf_rd_lines_0_data_0; // @[Cat.scala 33:{92,92}]
  wire [63:0] _GEN_38 = 2'h2 == wb_way_sel ? buf_rd_lines_2_data_0 : _GEN_37; // @[Cat.scala 33:{92,92}]
  wire [63:0] _GEN_39 = 2'h3 == wb_way_sel ? buf_rd_lines_3_data_0 : _GEN_38; // @[Cat.scala 33:{92,92}]
  wire [2:0] _state_T_2 = _T ? 3'h4 : 3'h1; // @[CacheCore.scala 390:38]
  wire [3:0] _state_T_5 = wb_done ? 4'h2 : 4'h8; // @[CacheCore.scala 392:38]
  wire [5:0] _state_T_8 = wb_req_done ? 6'h20 : 6'h10; // @[CacheCore.scala 394:38]
  wire [4:0] _state_T_10 = wb_index_done ? 5'h4 : 5'h10; // @[CacheCore.scala 396:40]
  wire [5:0] _state_T_11 = wb_ret_done ? {{1'd0}, _state_T_10} : 6'h20; // @[CacheCore.scala 395:38]
  wire [2:0] _state_T_12 = state[0] ? _state_T_2 : 3'h0; // @[Mux.scala 27:73]
  wire [3:0] _state_T_14 = state[2] ? _state_T_5 : 4'h0; // @[Mux.scala 27:73]
  wire [4:0] _state_T_15 = state[3] ? 5'h10 : 5'h0; // @[Mux.scala 27:73]
  wire [5:0] _state_T_16 = state[4] ? _state_T_8 : 6'h0; // @[Mux.scala 27:73]
  wire [5:0] _state_T_17 = state[5] ? _state_T_11 : 6'h0; // @[Mux.scala 27:73]
  wire [2:0] _GEN_41 = {{2'd0}, state[1]}; // @[Mux.scala 27:73]
  wire [2:0] _state_T_18 = _state_T_12 | _GEN_41; // @[Mux.scala 27:73]
  wire [3:0] _GEN_42 = {{1'd0}, _state_T_18}; // @[Mux.scala 27:73]
  wire [3:0] _state_T_19 = _GEN_42 | _state_T_14; // @[Mux.scala 27:73]
  wire [4:0] _GEN_43 = {{1'd0}, _state_T_19}; // @[Mux.scala 27:73]
  wire [4:0] _state_T_20 = _GEN_43 | _state_T_15; // @[Mux.scala 27:73]
  wire [5:0] _GEN_44 = {{1'd0}, _state_T_20}; // @[Mux.scala 27:73]
  wire [5:0] _state_T_21 = _GEN_44 | _state_T_16; // @[Mux.scala 27:73]
  wire [5:0] _state_T_22 = _state_T_21 | _state_T_17; // @[Mux.scala 27:73]
  assign io_req_ready = state[0]; // @[CacheCore.scala 338:26]
  assign io_ret = state[1]; // @[CacheCore.scala 339:26]
  assign io_meta_flush = state[1]; // @[CacheCore.scala 387:27]
  assign io_rd_en = state[2] & ~wb_done; // @[CacheCore.scala 365:26]
  assign io_rd_index = wb_index[4:0]; // @[CacheCore.scala 344:30]
  assign io_mem_out_req_valid = state[4] & _GEN_27; // @[CacheCore.scala 368:46]
  assign io_mem_out_req_bits_addr = {io_mem_out_req_bits_addr_hi,4'h0}; // @[Cat.scala 33:92]
  assign io_mem_out_req_bits_wdata = {_GEN_35,_GEN_39}; // @[Cat.scala 33:92]
  always @(posedge clock) begin
    if (reset) begin // @[CacheCore.scala 325:31]
      state <= 6'h1; // @[CacheCore.scala 325:31]
    end else begin
      state <= _state_T_22; // @[CacheCore.scala 389:11]
    end
    if (reset) begin // @[CacheCore.scala 329:31]
      wb_index <= 6'h0; // @[CacheCore.scala 329:31]
    end else if (_T) begin // @[CacheCore.scala 347:23]
      wb_index <= 6'h0; // @[CacheCore.scala 348:18]
    end else if (wb_index_done & wb_ret_done) begin // @[CacheCore.scala 349:47]
      wb_index <= _wb_index_T_1; // @[CacheCore.scala 350:18]
    end
    if (reset) begin // @[CacheCore.scala 330:31]
      wb_way <= 3'h0; // @[CacheCore.scala 330:31]
    end else if (state[2]) begin // @[CacheCore.scala 353:20]
      wb_way <= 3'h0; // @[CacheCore.scala 354:16]
    end else if (wb_req_done) begin // @[CacheCore.scala 355:30]
      wb_way <= _wb_way_T_1; // @[CacheCore.scala 356:16]
    end
    if (reset) begin // @[CacheCore.scala 335:31]
      wb_flag <= 1'h0; // @[CacheCore.scala 335:31]
    end else if (wb_req_done) begin // @[CacheCore.scala 381:23]
      wb_flag <= io_mem_out_req_valid; // @[CacheCore.scala 382:17]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_0_dirty <= 1'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_0_dirty <= io_rd_lines_0_dirty; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_0_tag <= 23'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_0_tag <= io_rd_lines_0_tag; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_0_data_0 <= 64'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_0_data_0 <= io_rd_lines_0_data_0; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_0_data_1 <= 64'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_0_data_1 <= io_rd_lines_0_data_1; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_1_dirty <= 1'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_1_dirty <= io_rd_lines_1_dirty; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_1_tag <= 23'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_1_tag <= io_rd_lines_1_tag; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_1_data_0 <= 64'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_1_data_0 <= io_rd_lines_1_data_0; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_1_data_1 <= 64'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_1_data_1 <= io_rd_lines_1_data_1; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_2_dirty <= 1'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_2_dirty <= io_rd_lines_2_dirty; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_2_tag <= 23'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_2_tag <= io_rd_lines_2_tag; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_2_data_0 <= 64'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_2_data_0 <= io_rd_lines_2_data_0; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_2_data_1 <= 64'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_2_data_1 <= io_rd_lines_2_data_1; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_3_dirty <= 1'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_3_dirty <= io_rd_lines_3_dirty; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_3_tag <= 23'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_3_tag <= io_rd_lines_3_tag; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_3_data_0 <= 64'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_3_data_0 <= io_rd_lines_3_data_0; // @[CacheCore.scala 362:29]
    end
    if (reset) begin // @[CacheCore.scala 336:31]
      buf_rd_lines_3_data_1 <= 64'h0; // @[CacheCore.scala 336:31]
    end else if (state[3]) begin // @[CacheCore.scala 360:5]
      buf_rd_lines_3_data_1 <= io_rd_lines_3_data_1; // @[CacheCore.scala 362:29]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  state = _RAND_0[5:0];
  _RAND_1 = {1{`RANDOM}};
  wb_index = _RAND_1[5:0];
  _RAND_2 = {1{`RANDOM}};
  wb_way = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  wb_flag = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  buf_rd_lines_0_dirty = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  buf_rd_lines_0_tag = _RAND_5[22:0];
  _RAND_6 = {2{`RANDOM}};
  buf_rd_lines_0_data_0 = _RAND_6[63:0];
  _RAND_7 = {2{`RANDOM}};
  buf_rd_lines_0_data_1 = _RAND_7[63:0];
  _RAND_8 = {1{`RANDOM}};
  buf_rd_lines_1_dirty = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  buf_rd_lines_1_tag = _RAND_9[22:0];
  _RAND_10 = {2{`RANDOM}};
  buf_rd_lines_1_data_0 = _RAND_10[63:0];
  _RAND_11 = {2{`RANDOM}};
  buf_rd_lines_1_data_1 = _RAND_11[63:0];
  _RAND_12 = {1{`RANDOM}};
  buf_rd_lines_2_dirty = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  buf_rd_lines_2_tag = _RAND_13[22:0];
  _RAND_14 = {2{`RANDOM}};
  buf_rd_lines_2_data_0 = _RAND_14[63:0];
  _RAND_15 = {2{`RANDOM}};
  buf_rd_lines_2_data_1 = _RAND_15[63:0];
  _RAND_16 = {1{`RANDOM}};
  buf_rd_lines_3_dirty = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  buf_rd_lines_3_tag = _RAND_17[22:0];
  _RAND_18 = {2{`RANDOM}};
  buf_rd_lines_3_data_0 = _RAND_18[63:0];
  _RAND_19 = {2{`RANDOM}};
  buf_rd_lines_3_data_1 = _RAND_19[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_CacheStage3(
  input          clock,
  input          reset,
  output [63:0]  io_cpu_rdata,
  output         io_cpu_valid,
  output         io_s2_to_s3_ready,
  input          io_s2_to_s3_valid,
  input          io_s2_to_s3_bits_wr,
  input  [63:0]  io_s2_to_s3_bits_wdata,
  input  [7:0]   io_s2_to_s3_bits_wstrb,
  input          io_s2_to_s3_bits_mthrough,
  input  [22:0]  io_s2_to_s3_bits_tag,
  input  [4:0]   io_s2_to_s3_bits_index,
  input  [3:0]   io_s2_to_s3_bits_offset,
  input  [1:0]   io_s2_to_s3_bits_size,
  input          io_s2_to_s3_bits_hit,
  input  [1:0]   io_s2_to_s3_bits_target_way,
  input          io_s2_to_s3_bits_target_line_valid,
  input          io_s2_to_s3_bits_target_line_dirty,
  input  [22:0]  io_s2_to_s3_bits_target_line_tag,
  input  [63:0]  io_s2_to_s3_bits_target_line_data_0,
  input  [63:0]  io_s2_to_s3_bits_target_line_data_1,
  input          io_s2_to_s3_bits_fencei,
  output         io_wt_en,
  output [1:0]   io_wt_way,
  output [4:0]   io_wt_index,
  output         io_wt_line_dirty,
  output [22:0]  io_wt_line_tag,
  output [63:0]  io_wt_line_data_0,
  output [63:0]  io_wt_line_data_1,
  input          io_mem_out_req_ready,
  output         io_mem_out_req_valid,
  output         io_mem_out_req_bits_wr,
  output [31:0]  io_mem_out_req_bits_addr,
  output [1:0]   io_mem_out_req_bits_size,
  output [127:0] io_mem_out_req_bits_wdata,
  output [7:0]   io_mem_out_req_bits_wstrb,
  output         io_mem_out_req_bits_mthrough,
  input  [63:0]  io_mem_out_ret_rdata,
  input          io_mem_out_ret_valid,
  input          io_mem_out_rlast,
  output         io_meta_flush,
  output         io_rd_en,
  output [4:0]   io_rd_index,
  input          io_rd_lines_0_dirty,
  input  [22:0]  io_rd_lines_0_tag,
  input  [63:0]  io_rd_lines_0_data_0,
  input  [63:0]  io_rd_lines_0_data_1,
  input          io_rd_lines_1_dirty,
  input  [22:0]  io_rd_lines_1_tag,
  input  [63:0]  io_rd_lines_1_data_0,
  input  [63:0]  io_rd_lines_1_data_1,
  input          io_rd_lines_2_dirty,
  input  [22:0]  io_rd_lines_2_tag,
  input  [63:0]  io_rd_lines_2_data_0,
  input  [63:0]  io_rd_lines_2_data_1,
  input          io_rd_lines_3_dirty,
  input  [22:0]  io_rd_lines_3_tag,
  input  [63:0]  io_rd_lines_3_data_0,
  input  [63:0]  io_rd_lines_3_data_1
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [63:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [63:0] _RAND_15;
  reg [63:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
`endif // RANDOMIZE_REG_INIT
  wire  fenceiModule_clock; // @[CacheCore.scala 152:30]
  wire  fenceiModule_reset; // @[CacheCore.scala 152:30]
  wire  fenceiModule_io_req_ready; // @[CacheCore.scala 152:30]
  wire  fenceiModule_io_req_valid; // @[CacheCore.scala 152:30]
  wire  fenceiModule_io_ret; // @[CacheCore.scala 152:30]
  wire  fenceiModule_io_meta_flush; // @[CacheCore.scala 152:30]
  wire  fenceiModule_io_rd_en; // @[CacheCore.scala 152:30]
  wire [4:0] fenceiModule_io_rd_index; // @[CacheCore.scala 152:30]
  wire  fenceiModule_io_rd_lines_0_dirty; // @[CacheCore.scala 152:30]
  wire [22:0] fenceiModule_io_rd_lines_0_tag; // @[CacheCore.scala 152:30]
  wire [63:0] fenceiModule_io_rd_lines_0_data_0; // @[CacheCore.scala 152:30]
  wire [63:0] fenceiModule_io_rd_lines_0_data_1; // @[CacheCore.scala 152:30]
  wire  fenceiModule_io_rd_lines_1_dirty; // @[CacheCore.scala 152:30]
  wire [22:0] fenceiModule_io_rd_lines_1_tag; // @[CacheCore.scala 152:30]
  wire [63:0] fenceiModule_io_rd_lines_1_data_0; // @[CacheCore.scala 152:30]
  wire [63:0] fenceiModule_io_rd_lines_1_data_1; // @[CacheCore.scala 152:30]
  wire  fenceiModule_io_rd_lines_2_dirty; // @[CacheCore.scala 152:30]
  wire [22:0] fenceiModule_io_rd_lines_2_tag; // @[CacheCore.scala 152:30]
  wire [63:0] fenceiModule_io_rd_lines_2_data_0; // @[CacheCore.scala 152:30]
  wire [63:0] fenceiModule_io_rd_lines_2_data_1; // @[CacheCore.scala 152:30]
  wire  fenceiModule_io_rd_lines_3_dirty; // @[CacheCore.scala 152:30]
  wire [22:0] fenceiModule_io_rd_lines_3_tag; // @[CacheCore.scala 152:30]
  wire [63:0] fenceiModule_io_rd_lines_3_data_0; // @[CacheCore.scala 152:30]
  wire [63:0] fenceiModule_io_rd_lines_3_data_1; // @[CacheCore.scala 152:30]
  wire  fenceiModule_io_mem_out_req_ready; // @[CacheCore.scala 152:30]
  wire  fenceiModule_io_mem_out_req_valid; // @[CacheCore.scala 152:30]
  wire [31:0] fenceiModule_io_mem_out_req_bits_addr; // @[CacheCore.scala 152:30]
  wire [127:0] fenceiModule_io_mem_out_req_bits_wdata; // @[CacheCore.scala 152:30]
  wire  fenceiModule_io_mem_out_ret_valid; // @[CacheCore.scala 152:30]
  reg  s3_valid; // @[CacheCore.scala 131:33]
  reg  buf_hit; // @[CacheCore.scala 137:33]
  reg [6:0] state; // @[CacheCore.scala 141:31]
  wire  hit = buf_hit & state[0] & s3_valid; // @[CacheCore.scala 178:53]
  reg  buf_wr; // @[CacheCore.scala 137:33]
  wire  _s3_ready_go_T = ~buf_wr; // @[CacheCore.scala 284:36]
  wire  _s3_ready_go_T_3 = state[4] & io_mem_out_ret_valid; // @[CacheCore.scala 285:30]
  wire  _s3_ready_go_T_4 = hit & ~buf_wr | _s3_ready_go_T_3; // @[CacheCore.scala 284:46]
  wire  _s3_ready_go_T_7 = _s3_ready_go_T_4 | state[5]; // @[CacheCore.scala 285:56]
  wire  _s3_ready_go_T_9 = state[6] & fenceiModule_io_ret; // @[CacheCore.scala 287:30]
  wire  s3_ready_go = _s3_ready_go_T_7 | _s3_ready_go_T_9; // @[CacheCore.scala 286:39]
  reg [63:0] buf_wdata; // @[CacheCore.scala 137:33]
  reg [7:0] buf_wstrb; // @[CacheCore.scala 137:33]
  reg  buf_mthrough; // @[CacheCore.scala 137:33]
  reg [22:0] buf_tag; // @[CacheCore.scala 137:33]
  reg [4:0] buf_index; // @[CacheCore.scala 137:33]
  reg [3:0] buf_offset; // @[CacheCore.scala 137:33]
  reg [1:0] buf_size; // @[CacheCore.scala 137:33]
  reg [1:0] buf_target_way; // @[CacheCore.scala 137:33]
  reg  buf_target_line_valid; // @[CacheCore.scala 137:33]
  reg  buf_target_line_dirty; // @[CacheCore.scala 137:33]
  reg [22:0] buf_target_line_tag; // @[CacheCore.scala 137:33]
  reg [63:0] buf_target_line_data_0; // @[CacheCore.scala 137:33]
  reg [63:0] buf_target_line_data_1; // @[CacheCore.scala 137:33]
  reg  buf_fencei; // @[CacheCore.scala 137:33]
  wire  _T = io_s2_to_s3_ready & io_s2_to_s3_valid; // @[Decoupled.scala 52:35]
  reg  cnt; // @[CacheCore.scala 142:31]
  wire  cpu_word_idx = buf_offset[3]; // @[CacheCore.scala 148:34]
  wire [31:0] cpu_req_addr = {buf_tag,buf_index,buf_offset}; // @[Cat.scala 33:92]
  wire  cpu_word_sel_0 = ~cpu_word_idx; // @[CacheCore.scala 167:78]
  wire [7:0] cpu_word_mask_vec_0 = buf_wstrb[0] ? 8'hff : 8'h0; // @[CacheCore.scala 168:68]
  wire [7:0] cpu_word_mask_vec_1 = buf_wstrb[1] ? 8'hff : 8'h0; // @[CacheCore.scala 168:68]
  wire [7:0] cpu_word_mask_vec_2 = buf_wstrb[2] ? 8'hff : 8'h0; // @[CacheCore.scala 168:68]
  wire [7:0] cpu_word_mask_vec_3 = buf_wstrb[3] ? 8'hff : 8'h0; // @[CacheCore.scala 168:68]
  wire [7:0] cpu_word_mask_vec_4 = buf_wstrb[4] ? 8'hff : 8'h0; // @[CacheCore.scala 168:68]
  wire [7:0] cpu_word_mask_vec_5 = buf_wstrb[5] ? 8'hff : 8'h0; // @[CacheCore.scala 168:68]
  wire [7:0] cpu_word_mask_vec_6 = buf_wstrb[6] ? 8'hff : 8'h0; // @[CacheCore.scala 168:68]
  wire [7:0] cpu_word_mask_vec_7 = buf_wstrb[7] ? 8'hff : 8'h0; // @[CacheCore.scala 168:68]
  wire [63:0] cpu_word_mask = {cpu_word_mask_vec_7,cpu_word_mask_vec_6,cpu_word_mask_vec_5,cpu_word_mask_vec_4,
    cpu_word_mask_vec_3,cpu_word_mask_vec_2,cpu_word_mask_vec_1,cpu_word_mask_vec_0}; // @[Cat.scala 33:92]
  wire [63:0] wdata_src_0 = state[0] ? buf_target_line_data_0 : io_mem_out_ret_rdata; // @[CacheCore.scala 173:37]
  wire [63:0] _masked_wtline_data_0_T = ~cpu_word_mask; // @[CacheCore.scala 174:50]
  wire [63:0] _masked_wtline_data_0_T_1 = wdata_src_0 & _masked_wtline_data_0_T; // @[CacheCore.scala 174:48]
  wire [63:0] _masked_wtline_data_0_T_2 = buf_wdata & cpu_word_mask; // @[CacheCore.scala 174:79]
  wire [63:0] masked_wtline_data_0 = _masked_wtline_data_0_T_1 | _masked_wtline_data_0_T_2; // @[CacheCore.scala 174:66]
  wire [63:0] wdata_src_1 = state[0] ? buf_target_line_data_1 : io_mem_out_ret_rdata; // @[CacheCore.scala 173:37]
  wire [63:0] _masked_wtline_data_1_T_1 = wdata_src_1 & _masked_wtline_data_0_T; // @[CacheCore.scala 174:48]
  wire [63:0] masked_wtline_data_1 = _masked_wtline_data_1_T_1 | _masked_wtline_data_0_T_2; // @[CacheCore.scala 174:66]
  wire  write_hit = hit & buf_wr; // @[CacheCore.scala 180:27]
  wire  _wb_en_T_1 = ~hit; // @[CacheCore.scala 183:71]
  wire  wb_en = buf_target_line_valid & buf_target_line_dirty & ~hit & state[0] & s3_valid & ~buf_mthrough; // @[CacheCore.scala 183:98]
  wire [31:0] wb_addr = {buf_target_line_tag,buf_index,cpu_word_idx,3'h0}; // @[Cat.scala 33:92]
  wire  burst_last = io_mem_out_ret_valid & (state[1] | io_mem_out_rlast); // @[CacheCore.scala 188:44]
  wire  refill_come = state[3] & io_mem_out_ret_valid; // @[CacheCore.scala 191:35]
  wire  cnt_hit_0 = ~cnt; // @[CacheCore.scala 201:64]
  wire  _write_line_sel_0_0_T = ~cpu_word_sel_0; // @[CacheCore.scala 254:47]
  wire  write_line_sel_0_0 = write_hit & ~cpu_word_sel_0 | state[3] & ~cnt_hit_0; // @[CacheCore.scala 254:65]
  wire [63:0] _write_line_data_0_T = write_line_sel_0_0 ? buf_target_line_data_0 : 64'h0; // @[Mux.scala 27:73]
  wire  _write_line_sel_0_1_T_1 = state[3] & cnt_hit_0; // @[CacheCore.scala 256:42]
  wire  write_line_sel_0_1 = state[3] & cnt_hit_0 & (_s3_ready_go_T | buf_wr & _write_line_sel_0_0_T); // @[CacheCore.scala 256:56]
  wire [63:0] _write_line_data_0_T_1 = write_line_sel_0_1 ? io_mem_out_ret_rdata : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _write_line_data_0_T_3 = _write_line_data_0_T | _write_line_data_0_T_1; // @[Mux.scala 27:73]
  wire  _write_line_sel_0_2_T = write_hit & cpu_word_sel_0; // @[CacheCore.scala 258:44]
  wire  _write_line_sel_0_2_T_5 = _write_line_sel_0_1_T_1 & cpu_word_sel_0 & buf_wr; // @[CacheCore.scala 259:76]
  wire  write_line_sel_0_2 = write_hit & cpu_word_sel_0 | _write_line_sel_0_2_T_5; // @[CacheCore.scala 258:64]
  wire [63:0] _write_line_data_0_T_2 = write_line_sel_0_2 ? masked_wtline_data_0 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] write_line_data_0 = _write_line_data_0_T_3 | _write_line_data_0_T_2; // @[Mux.scala 27:73]
  wire  write_line_sel_1_0 = _write_line_sel_0_2_T | _write_line_sel_0_1_T_1; // @[CacheCore.scala 254:65]
  wire [63:0] _write_line_data_1_T = write_line_sel_1_0 ? buf_target_line_data_1 : 64'h0; // @[Mux.scala 27:73]
  wire  _write_line_sel_1_1_T_1 = state[3] & cnt; // @[CacheCore.scala 256:42]
  wire  write_line_sel_1_1 = state[3] & cnt & (_s3_ready_go_T | buf_wr & cpu_word_sel_0); // @[CacheCore.scala 256:56]
  wire [63:0] _write_line_data_1_T_1 = write_line_sel_1_1 ? io_mem_out_ret_rdata : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _write_line_data_1_T_3 = _write_line_data_1_T | _write_line_data_1_T_1; // @[Mux.scala 27:73]
  wire  _write_line_sel_1_2_T_5 = _write_line_sel_1_1_T_1 & cpu_word_idx & buf_wr; // @[CacheCore.scala 259:76]
  wire  write_line_sel_1_2 = write_hit & cpu_word_idx | _write_line_sel_1_2_T_5; // @[CacheCore.scala 258:64]
  wire [63:0] _write_line_data_1_T_2 = write_line_sel_1_2 ? masked_wtline_data_1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] write_line_data_1 = _write_line_data_1_T_3 | _write_line_data_1_T_2; // @[Mux.scala 27:73]
  wire  _T_4 = io_mem_out_req_ready & io_mem_out_req_valid; // @[Decoupled.scala 52:35]
  wire  _cnt_T_3 = cnt ? 1'h0 : cnt + 1'h1; // @[CacheCore.scala 209:19]
  wire  stage3_mem_req_valid = s3_valid & (state[0] & _wb_en_T_1 & ~buf_fencei | state[2]); // @[CacheCore.scala 215:41]
  wire  stage3_mem_req_wr = wb_en | buf_mthrough & buf_wr; // @[CacheCore.scala 216:38]
  wire [31:0] stage3_mem_req_addr = wb_en ? wb_addr : cpu_req_addr; // @[CacheCore.scala 217:35]
  wire [1:0] stage3_mem_req_size = buf_mthrough ? buf_size : 2'h3; // @[CacheCore.scala 218:35]
  wire [63:0] mmio_wblock_1 = cpu_word_idx ? buf_wdata : 64'h0; // @[CacheCore.scala 238:30]
  wire [63:0] mmio_wblock_0 = cpu_word_sel_0 ? buf_wdata : 64'h0; // @[CacheCore.scala 238:30]
  wire [127:0] _stage3_mem_req_wdata_T_1 = {mmio_wblock_1,mmio_wblock_0}; // @[Cat.scala 33:92]
  wire [127:0] _stage3_mem_req_wdata_T_2 = {buf_target_line_data_1,buf_target_line_data_0}; // @[Cat.scala 33:92]
  wire [127:0] stage3_mem_req_wdata = buf_mthrough ? _stage3_mem_req_wdata_T_1 : _stage3_mem_req_wdata_T_2; // @[CacheCore.scala 219:35]
  wire [7:0] stage3_mem_req_wstrb = buf_mthrough ? buf_wstrb : 8'hff; // @[CacheCore.scala 221:35]
  wire  _io_wt_en_T_3 = state[3] & burst_last; // @[CacheCore.scala 243:67]
  wire  _state_T_2 = fenceiModule_io_req_ready & fenceiModule_io_req_valid; // @[Decoupled.scala 52:35]
  wire [6:0] _state_T_3 = _state_T_2 ? 7'h40 : 7'h1; // @[CacheCore.scala 269:66]
  wire [5:0] _state_T_5 = buf_wr ? 6'h20 : 6'h1; // @[CacheCore.scala 270:57]
  wire [3:0] _state_T_10 = wb_en ? 4'h2 : 4'h8; // @[CacheCore.scala 273:64]
  wire [4:0] _state_T_11 = buf_mthrough ? 5'h10 : {{1'd0}, _state_T_10}; // @[CacheCore.scala 272:60]
  wire [4:0] _state_T_12 = ~_T_4 ? 5'h1 : _state_T_11; // @[CacheCore.scala 271:56]
  wire [5:0] _state_T_13 = hit ? _state_T_5 : {{1'd0}, _state_T_12}; // @[CacheCore.scala 270:48]
  wire [6:0] _state_T_14 = buf_fencei ? _state_T_3 : {{1'd0}, _state_T_13}; // @[CacheCore.scala 269:41]
  wire [2:0] _state_T_16 = burst_last ? 3'h4 : 3'h2; // @[CacheCore.scala 277:41]
  wire [3:0] _state_T_19 = _T_4 ? 4'h8 : 4'h4; // @[CacheCore.scala 278:41]
  wire [5:0] _state_T_21 = burst_last ? 6'h20 : 6'h8; // @[CacheCore.scala 279:41]
  wire [4:0] _state_T_23 = io_mem_out_ret_valid ? 5'h1 : 5'h10; // @[CacheCore.scala 280:41]
  wire [6:0] _state_T_26 = fenceiModule_io_ret ? 7'h1 : 7'h40; // @[CacheCore.scala 282:41]
  wire [6:0] _state_T_27 = state[0] ? _state_T_14 : 7'h0; // @[Mux.scala 27:73]
  wire [2:0] _state_T_28 = state[1] ? _state_T_16 : 3'h0; // @[Mux.scala 27:73]
  wire [3:0] _state_T_29 = state[2] ? _state_T_19 : 4'h0; // @[Mux.scala 27:73]
  wire [5:0] _state_T_30 = state[3] ? _state_T_21 : 6'h0; // @[Mux.scala 27:73]
  wire [4:0] _state_T_31 = state[4] ? _state_T_23 : 5'h0; // @[Mux.scala 27:73]
  wire [6:0] _state_T_33 = state[6] ? _state_T_26 : 7'h0; // @[Mux.scala 27:73]
  wire [6:0] _GEN_26 = {{4'd0}, _state_T_28}; // @[Mux.scala 27:73]
  wire [6:0] _state_T_34 = _state_T_27 | _GEN_26; // @[Mux.scala 27:73]
  wire [6:0] _GEN_27 = {{3'd0}, _state_T_29}; // @[Mux.scala 27:73]
  wire [6:0] _state_T_35 = _state_T_34 | _GEN_27; // @[Mux.scala 27:73]
  wire [6:0] _GEN_28 = {{1'd0}, _state_T_30}; // @[Mux.scala 27:73]
  wire [6:0] _state_T_36 = _state_T_35 | _GEN_28; // @[Mux.scala 27:73]
  wire [6:0] _GEN_29 = {{2'd0}, _state_T_31}; // @[Mux.scala 27:73]
  wire [6:0] _state_T_37 = _state_T_36 | _GEN_29; // @[Mux.scala 27:73]
  wire [6:0] _GEN_30 = {{6'd0}, state[5]}; // @[Mux.scala 27:73]
  wire [6:0] _state_T_38 = _state_T_37 | _GEN_30; // @[Mux.scala 27:73]
  wire [6:0] _state_T_39 = _state_T_38 | _state_T_33; // @[Mux.scala 27:73]
  wire [63:0] _GEN_23 = cpu_word_idx ? write_line_data_1 : write_line_data_0; // @[CacheCore.scala 291:{28,28}]
  wire [63:0] _io_cpu_rdata_T_1 = state[4] ? io_mem_out_ret_rdata : _GEN_23; // @[CacheCore.scala 291:28]
  wire [63:0] _GEN_25 = cpu_word_idx ? buf_target_line_data_1 : buf_target_line_data_0; // @[CacheCore.scala 290:{26,26}]
  wire  _io_cpu_valid_T_6 = state[4] ? io_mem_out_ret_valid : _io_wt_en_T_3; // @[CacheCore.scala 293:58]
  wire  _io_cpu_valid_T_7 = hit | _io_cpu_valid_T_6; // @[CacheCore.scala 293:44]
  wire  _io_cpu_valid_T_8 = buf_fencei ? _s3_ready_go_T_9 : _io_cpu_valid_T_7; // @[CacheCore.scala 292:38]
  ysyx_22051110_CacheFencei fenceiModule ( // @[CacheCore.scala 152:30]
    .clock(fenceiModule_clock),
    .reset(fenceiModule_reset),
    .io_req_ready(fenceiModule_io_req_ready),
    .io_req_valid(fenceiModule_io_req_valid),
    .io_ret(fenceiModule_io_ret),
    .io_meta_flush(fenceiModule_io_meta_flush),
    .io_rd_en(fenceiModule_io_rd_en),
    .io_rd_index(fenceiModule_io_rd_index),
    .io_rd_lines_0_dirty(fenceiModule_io_rd_lines_0_dirty),
    .io_rd_lines_0_tag(fenceiModule_io_rd_lines_0_tag),
    .io_rd_lines_0_data_0(fenceiModule_io_rd_lines_0_data_0),
    .io_rd_lines_0_data_1(fenceiModule_io_rd_lines_0_data_1),
    .io_rd_lines_1_dirty(fenceiModule_io_rd_lines_1_dirty),
    .io_rd_lines_1_tag(fenceiModule_io_rd_lines_1_tag),
    .io_rd_lines_1_data_0(fenceiModule_io_rd_lines_1_data_0),
    .io_rd_lines_1_data_1(fenceiModule_io_rd_lines_1_data_1),
    .io_rd_lines_2_dirty(fenceiModule_io_rd_lines_2_dirty),
    .io_rd_lines_2_tag(fenceiModule_io_rd_lines_2_tag),
    .io_rd_lines_2_data_0(fenceiModule_io_rd_lines_2_data_0),
    .io_rd_lines_2_data_1(fenceiModule_io_rd_lines_2_data_1),
    .io_rd_lines_3_dirty(fenceiModule_io_rd_lines_3_dirty),
    .io_rd_lines_3_tag(fenceiModule_io_rd_lines_3_tag),
    .io_rd_lines_3_data_0(fenceiModule_io_rd_lines_3_data_0),
    .io_rd_lines_3_data_1(fenceiModule_io_rd_lines_3_data_1),
    .io_mem_out_req_ready(fenceiModule_io_mem_out_req_ready),
    .io_mem_out_req_valid(fenceiModule_io_mem_out_req_valid),
    .io_mem_out_req_bits_addr(fenceiModule_io_mem_out_req_bits_addr),
    .io_mem_out_req_bits_wdata(fenceiModule_io_mem_out_req_bits_wdata),
    .io_mem_out_ret_valid(fenceiModule_io_mem_out_ret_valid)
  );
  assign io_cpu_rdata = hit ? _GEN_25 : _io_cpu_rdata_T_1; // @[CacheCore.scala 290:26]
  assign io_cpu_valid = s3_valid & _io_cpu_valid_T_8; // @[CacheCore.scala 292:32]
  assign io_s2_to_s3_ready = ~s3_valid | s3_ready_go; // @[CacheCore.scala 132:37]
  assign io_wt_en = s3_valid & (state[0] & write_hit | state[3] & burst_last); // @[CacheCore.scala 243:29]
  assign io_wt_way = buf_target_way; // @[CacheCore.scala 244:17]
  assign io_wt_index = buf_index; // @[CacheCore.scala 245:17]
  assign io_wt_line_dirty = buf_wr; // @[CacheCore.scala 145:28 248:22]
  assign io_wt_line_tag = buf_tag; // @[CacheCore.scala 145:28 249:22]
  assign io_wt_line_data_0 = _write_line_data_0_T_3 | _write_line_data_0_T_2; // @[Mux.scala 27:73]
  assign io_wt_line_data_1 = _write_line_data_1_T_3 | _write_line_data_1_T_2; // @[Mux.scala 27:73]
  assign io_mem_out_req_valid = state[6] ? fenceiModule_io_mem_out_req_valid : stage3_mem_req_valid; // @[CacheCore.scala 225:40]
  assign io_mem_out_req_bits_wr = state[6] | stage3_mem_req_wr; // @[CacheCore.scala 227:40]
  assign io_mem_out_req_bits_addr = state[6] ? fenceiModule_io_mem_out_req_bits_addr : stage3_mem_req_addr; // @[CacheCore.scala 228:40]
  assign io_mem_out_req_bits_size = state[6] ? 2'h3 : stage3_mem_req_size; // @[CacheCore.scala 229:40]
  assign io_mem_out_req_bits_wdata = state[6] ? fenceiModule_io_mem_out_req_bits_wdata : stage3_mem_req_wdata; // @[CacheCore.scala 230:40]
  assign io_mem_out_req_bits_wstrb = state[6] ? 8'hff : stage3_mem_req_wstrb; // @[CacheCore.scala 231:40]
  assign io_mem_out_req_bits_mthrough = state[6] ? 1'h0 : buf_mthrough; // @[CacheCore.scala 232:40]
  assign io_meta_flush = fenceiModule_io_meta_flush; // @[CacheCore.scala 160:19]
  assign io_rd_en = fenceiModule_io_rd_en; // @[CacheCore.scala 158:19]
  assign io_rd_index = fenceiModule_io_rd_index; // @[CacheCore.scala 158:19]
  assign fenceiModule_clock = clock;
  assign fenceiModule_reset = reset;
  assign fenceiModule_io_req_valid = state[0] & s3_valid & buf_fencei; // @[CacheCore.scala 153:62]
  assign fenceiModule_io_rd_lines_0_dirty = io_rd_lines_0_dirty; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_0_tag = io_rd_lines_0_tag; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_0_data_0 = io_rd_lines_0_data_0; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_0_data_1 = io_rd_lines_0_data_1; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_1_dirty = io_rd_lines_1_dirty; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_1_tag = io_rd_lines_1_tag; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_1_data_0 = io_rd_lines_1_data_0; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_1_data_1 = io_rd_lines_1_data_1; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_2_dirty = io_rd_lines_2_dirty; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_2_tag = io_rd_lines_2_tag; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_2_data_0 = io_rd_lines_2_data_0; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_2_data_1 = io_rd_lines_2_data_1; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_3_dirty = io_rd_lines_3_dirty; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_3_tag = io_rd_lines_3_tag; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_3_data_0 = io_rd_lines_3_data_0; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_rd_lines_3_data_1 = io_rd_lines_3_data_1; // @[CacheCore.scala 154:39]
  assign fenceiModule_io_mem_out_req_ready = io_mem_out_req_ready; // @[CacheCore.scala 155:39]
  assign fenceiModule_io_mem_out_ret_valid = io_mem_out_ret_valid; // @[CacheCore.scala 156:39]
  always @(posedge clock) begin
    if (reset) begin // @[CacheCore.scala 131:33]
      s3_valid <= 1'h0; // @[CacheCore.scala 131:33]
    end else if (io_s2_to_s3_ready) begin // @[CacheCore.scala 133:28]
      s3_valid <= io_s2_to_s3_valid; // @[CacheCore.scala 134:18]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_hit <= 1'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_hit <= io_s2_to_s3_bits_hit; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 141:31]
      state <= 7'h1; // @[CacheCore.scala 141:31]
    end else begin
      state <= _state_T_39; // @[CacheCore.scala 268:11]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_wr <= 1'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_wr <= io_s2_to_s3_bits_wr; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_wdata <= 64'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_wdata <= io_s2_to_s3_bits_wdata; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_wstrb <= 8'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_wstrb <= io_s2_to_s3_bits_wstrb; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_mthrough <= 1'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_mthrough <= io_s2_to_s3_bits_mthrough; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_tag <= 23'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_tag <= io_s2_to_s3_bits_tag; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_index <= 5'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_index <= io_s2_to_s3_bits_index; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_offset <= 4'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_offset <= io_s2_to_s3_bits_offset; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_size <= 2'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_size <= io_s2_to_s3_bits_size; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_target_way <= 2'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_target_way <= io_s2_to_s3_bits_target_way; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_target_line_valid <= 1'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_target_line_valid <= io_s2_to_s3_bits_target_line_valid; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_target_line_dirty <= 1'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_target_line_dirty <= io_s2_to_s3_bits_target_line_dirty; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_target_line_tag <= 23'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_target_line_tag <= io_s2_to_s3_bits_target_line_tag; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_target_line_data_0 <= 64'h0; // @[CacheCore.scala 137:33]
    end else if (refill_come & cnt_hit_0) begin // @[CacheCore.scala 196:41]
      buf_target_line_data_0 <= write_line_data_0; // @[CacheCore.scala 197:37]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_target_line_data_0 <= io_s2_to_s3_bits_target_line_data_0; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_target_line_data_1 <= 64'h0; // @[CacheCore.scala 137:33]
    end else if (refill_come & cnt) begin // @[CacheCore.scala 196:41]
      buf_target_line_data_1 <= write_line_data_1; // @[CacheCore.scala 197:37]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_target_line_data_1 <= io_s2_to_s3_bits_target_line_data_1; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 137:33]
      buf_fencei <= 1'h0; // @[CacheCore.scala 137:33]
    end else if (_T) begin // @[CacheCore.scala 138:27]
      buf_fencei <= io_s2_to_s3_bits_fencei; // @[CacheCore.scala 139:13]
    end
    if (reset) begin // @[CacheCore.scala 142:31]
      cnt <= 1'h0; // @[CacheCore.scala 142:31]
    end else if (wb_en & _T_4) begin // @[CacheCore.scala 204:49]
      cnt <= 1'h0; // @[CacheCore.scala 205:13]
    end else if ((state[2] | state[0] & ~wb_en) & _T_4) begin // @[CacheCore.scala 206:82]
      cnt <= cpu_word_idx; // @[CacheCore.scala 207:13]
    end else if (io_mem_out_ret_valid) begin // @[CacheCore.scala 208:38]
      cnt <= _cnt_T_3; // @[CacheCore.scala 209:13]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  s3_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buf_hit = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  state = _RAND_2[6:0];
  _RAND_3 = {1{`RANDOM}};
  buf_wr = _RAND_3[0:0];
  _RAND_4 = {2{`RANDOM}};
  buf_wdata = _RAND_4[63:0];
  _RAND_5 = {1{`RANDOM}};
  buf_wstrb = _RAND_5[7:0];
  _RAND_6 = {1{`RANDOM}};
  buf_mthrough = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  buf_tag = _RAND_7[22:0];
  _RAND_8 = {1{`RANDOM}};
  buf_index = _RAND_8[4:0];
  _RAND_9 = {1{`RANDOM}};
  buf_offset = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  buf_size = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  buf_target_way = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  buf_target_line_valid = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  buf_target_line_dirty = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  buf_target_line_tag = _RAND_14[22:0];
  _RAND_15 = {2{`RANDOM}};
  buf_target_line_data_0 = _RAND_15[63:0];
  _RAND_16 = {2{`RANDOM}};
  buf_target_line_data_1 = _RAND_16[63:0];
  _RAND_17 = {1{`RANDOM}};
  buf_fencei = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  cnt = _RAND_18[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_CacheMetaRam(
  input         clock,
  input         reset,
  input         io_flush,
  input         io_en,
  input         io_wr,
  input  [1:0]  io_way,
  input  [4:0]  io_index,
  output        io_out_0_valid,
  output        io_out_0_dirty,
  output [22:0] io_out_0_tag,
  output        io_out_1_valid,
  output        io_out_1_dirty,
  output [22:0] io_out_1_tag,
  output        io_out_2_valid,
  output        io_out_2_dirty,
  output [22:0] io_out_2_tag,
  output        io_out_3_valid,
  output        io_out_3_dirty,
  output [22:0] io_out_3_tag,
  input         io_in_dirty,
  input  [22:0] io_in_tag
);
  wire  ysyx_22051110_CacheMetaRamV_clock; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_reset; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_flush; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_valid; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_dirty; // @[CacheRam.scala 28:48]
  wire [22:0] ysyx_22051110_CacheMetaRamV_tag; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_en; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_wr; // @[CacheRam.scala 28:48]
  wire [5:0] ysyx_22051110_CacheMetaRamV_addr; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_wvalid; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_wdirty; // @[CacheRam.scala 28:48]
  wire [22:0] ysyx_22051110_CacheMetaRamV_wtag; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_1_clock; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_1_reset; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_1_flush; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_1_valid; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_1_dirty; // @[CacheRam.scala 28:48]
  wire [22:0] ysyx_22051110_CacheMetaRamV_1_tag; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_1_en; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_1_wr; // @[CacheRam.scala 28:48]
  wire [5:0] ysyx_22051110_CacheMetaRamV_1_addr; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_1_wvalid; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_1_wdirty; // @[CacheRam.scala 28:48]
  wire [22:0] ysyx_22051110_CacheMetaRamV_1_wtag; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_2_clock; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_2_reset; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_2_flush; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_2_valid; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_2_dirty; // @[CacheRam.scala 28:48]
  wire [22:0] ysyx_22051110_CacheMetaRamV_2_tag; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_2_en; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_2_wr; // @[CacheRam.scala 28:48]
  wire [5:0] ysyx_22051110_CacheMetaRamV_2_addr; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_2_wvalid; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_2_wdirty; // @[CacheRam.scala 28:48]
  wire [22:0] ysyx_22051110_CacheMetaRamV_2_wtag; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_3_clock; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_3_reset; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_3_flush; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_3_valid; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_3_dirty; // @[CacheRam.scala 28:48]
  wire [22:0] ysyx_22051110_CacheMetaRamV_3_tag; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_3_en; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_3_wr; // @[CacheRam.scala 28:48]
  wire [5:0] ysyx_22051110_CacheMetaRamV_3_addr; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_3_wvalid; // @[CacheRam.scala 28:48]
  wire  ysyx_22051110_CacheMetaRamV_3_wdirty; // @[CacheRam.scala 28:48]
  wire [22:0] ysyx_22051110_CacheMetaRamV_3_wtag; // @[CacheRam.scala 28:48]
  wire  hit_array_0 = io_way == 2'h0 | ~io_wr; // @[CacheRam.scala 31:48]
  wire  hit_array_1 = io_way == 2'h1 | ~io_wr; // @[CacheRam.scala 31:48]
  wire  hit_array_2 = io_way == 2'h2 | ~io_wr; // @[CacheRam.scala 31:48]
  wire  hit_array_3 = io_way == 2'h3 | ~io_wr; // @[CacheRam.scala 31:48]
  ysyx_22051110_CacheMetaRamV ysyx_22051110_CacheMetaRamV ( // @[CacheRam.scala 28:48]
    .clock(ysyx_22051110_CacheMetaRamV_clock),
    .reset(ysyx_22051110_CacheMetaRamV_reset),
    .flush(ysyx_22051110_CacheMetaRamV_flush),
    .valid(ysyx_22051110_CacheMetaRamV_valid),
    .dirty(ysyx_22051110_CacheMetaRamV_dirty),
    .tag(ysyx_22051110_CacheMetaRamV_tag),
    .en(ysyx_22051110_CacheMetaRamV_en),
    .wr(ysyx_22051110_CacheMetaRamV_wr),
    .addr(ysyx_22051110_CacheMetaRamV_addr),
    .wvalid(ysyx_22051110_CacheMetaRamV_wvalid),
    .wdirty(ysyx_22051110_CacheMetaRamV_wdirty),
    .wtag(ysyx_22051110_CacheMetaRamV_wtag)
  );
  ysyx_22051110_CacheMetaRamV ysyx_22051110_CacheMetaRamV_1 ( // @[CacheRam.scala 28:48]
    .clock(ysyx_22051110_CacheMetaRamV_1_clock),
    .reset(ysyx_22051110_CacheMetaRamV_1_reset),
    .flush(ysyx_22051110_CacheMetaRamV_1_flush),
    .valid(ysyx_22051110_CacheMetaRamV_1_valid),
    .dirty(ysyx_22051110_CacheMetaRamV_1_dirty),
    .tag(ysyx_22051110_CacheMetaRamV_1_tag),
    .en(ysyx_22051110_CacheMetaRamV_1_en),
    .wr(ysyx_22051110_CacheMetaRamV_1_wr),
    .addr(ysyx_22051110_CacheMetaRamV_1_addr),
    .wvalid(ysyx_22051110_CacheMetaRamV_1_wvalid),
    .wdirty(ysyx_22051110_CacheMetaRamV_1_wdirty),
    .wtag(ysyx_22051110_CacheMetaRamV_1_wtag)
  );
  ysyx_22051110_CacheMetaRamV ysyx_22051110_CacheMetaRamV_2 ( // @[CacheRam.scala 28:48]
    .clock(ysyx_22051110_CacheMetaRamV_2_clock),
    .reset(ysyx_22051110_CacheMetaRamV_2_reset),
    .flush(ysyx_22051110_CacheMetaRamV_2_flush),
    .valid(ysyx_22051110_CacheMetaRamV_2_valid),
    .dirty(ysyx_22051110_CacheMetaRamV_2_dirty),
    .tag(ysyx_22051110_CacheMetaRamV_2_tag),
    .en(ysyx_22051110_CacheMetaRamV_2_en),
    .wr(ysyx_22051110_CacheMetaRamV_2_wr),
    .addr(ysyx_22051110_CacheMetaRamV_2_addr),
    .wvalid(ysyx_22051110_CacheMetaRamV_2_wvalid),
    .wdirty(ysyx_22051110_CacheMetaRamV_2_wdirty),
    .wtag(ysyx_22051110_CacheMetaRamV_2_wtag)
  );
  ysyx_22051110_CacheMetaRamV ysyx_22051110_CacheMetaRamV_3 ( // @[CacheRam.scala 28:48]
    .clock(ysyx_22051110_CacheMetaRamV_3_clock),
    .reset(ysyx_22051110_CacheMetaRamV_3_reset),
    .flush(ysyx_22051110_CacheMetaRamV_3_flush),
    .valid(ysyx_22051110_CacheMetaRamV_3_valid),
    .dirty(ysyx_22051110_CacheMetaRamV_3_dirty),
    .tag(ysyx_22051110_CacheMetaRamV_3_tag),
    .en(ysyx_22051110_CacheMetaRamV_3_en),
    .wr(ysyx_22051110_CacheMetaRamV_3_wr),
    .addr(ysyx_22051110_CacheMetaRamV_3_addr),
    .wvalid(ysyx_22051110_CacheMetaRamV_3_wvalid),
    .wdirty(ysyx_22051110_CacheMetaRamV_3_wdirty),
    .wtag(ysyx_22051110_CacheMetaRamV_3_wtag)
  );
  assign io_out_0_valid = ysyx_22051110_CacheMetaRamV_valid; // @[CacheRam.scala 41:30]
  assign io_out_0_dirty = ysyx_22051110_CacheMetaRamV_dirty; // @[CacheRam.scala 42:30]
  assign io_out_0_tag = ysyx_22051110_CacheMetaRamV_tag; // @[CacheRam.scala 43:30]
  assign io_out_1_valid = ysyx_22051110_CacheMetaRamV_1_valid; // @[CacheRam.scala 41:30]
  assign io_out_1_dirty = ysyx_22051110_CacheMetaRamV_1_dirty; // @[CacheRam.scala 42:30]
  assign io_out_1_tag = ysyx_22051110_CacheMetaRamV_1_tag; // @[CacheRam.scala 43:30]
  assign io_out_2_valid = ysyx_22051110_CacheMetaRamV_2_valid; // @[CacheRam.scala 41:30]
  assign io_out_2_dirty = ysyx_22051110_CacheMetaRamV_2_dirty; // @[CacheRam.scala 42:30]
  assign io_out_2_tag = ysyx_22051110_CacheMetaRamV_2_tag; // @[CacheRam.scala 43:30]
  assign io_out_3_valid = ysyx_22051110_CacheMetaRamV_3_valid; // @[CacheRam.scala 41:30]
  assign io_out_3_dirty = ysyx_22051110_CacheMetaRamV_3_dirty; // @[CacheRam.scala 42:30]
  assign io_out_3_tag = ysyx_22051110_CacheMetaRamV_3_tag; // @[CacheRam.scala 43:30]
  assign ysyx_22051110_CacheMetaRamV_clock = clock; // @[CacheRam.scala 32:30]
  assign ysyx_22051110_CacheMetaRamV_reset = reset; // @[CacheRam.scala 33:30]
  assign ysyx_22051110_CacheMetaRamV_flush = io_flush; // @[CacheRam.scala 34:30]
  assign ysyx_22051110_CacheMetaRamV_en = hit_array_0 & io_en; // @[CacheRam.scala 35:46]
  assign ysyx_22051110_CacheMetaRamV_wr = io_wr; // @[CacheRam.scala 36:30]
  assign ysyx_22051110_CacheMetaRamV_addr = {{1'd0}, io_index}; // @[CacheRam.scala 37:30]
  assign ysyx_22051110_CacheMetaRamV_wvalid = 1'h1; // @[CacheRam.scala 38:30]
  assign ysyx_22051110_CacheMetaRamV_wdirty = io_in_dirty; // @[CacheRam.scala 39:30]
  assign ysyx_22051110_CacheMetaRamV_wtag = io_in_tag; // @[CacheRam.scala 40:30]
  assign ysyx_22051110_CacheMetaRamV_1_clock = clock; // @[CacheRam.scala 32:30]
  assign ysyx_22051110_CacheMetaRamV_1_reset = reset; // @[CacheRam.scala 33:30]
  assign ysyx_22051110_CacheMetaRamV_1_flush = io_flush; // @[CacheRam.scala 34:30]
  assign ysyx_22051110_CacheMetaRamV_1_en = hit_array_1 & io_en; // @[CacheRam.scala 35:46]
  assign ysyx_22051110_CacheMetaRamV_1_wr = io_wr; // @[CacheRam.scala 36:30]
  assign ysyx_22051110_CacheMetaRamV_1_addr = {{1'd0}, io_index}; // @[CacheRam.scala 37:30]
  assign ysyx_22051110_CacheMetaRamV_1_wvalid = 1'h1; // @[CacheRam.scala 38:30]
  assign ysyx_22051110_CacheMetaRamV_1_wdirty = io_in_dirty; // @[CacheRam.scala 39:30]
  assign ysyx_22051110_CacheMetaRamV_1_wtag = io_in_tag; // @[CacheRam.scala 40:30]
  assign ysyx_22051110_CacheMetaRamV_2_clock = clock; // @[CacheRam.scala 32:30]
  assign ysyx_22051110_CacheMetaRamV_2_reset = reset; // @[CacheRam.scala 33:30]
  assign ysyx_22051110_CacheMetaRamV_2_flush = io_flush; // @[CacheRam.scala 34:30]
  assign ysyx_22051110_CacheMetaRamV_2_en = hit_array_2 & io_en; // @[CacheRam.scala 35:46]
  assign ysyx_22051110_CacheMetaRamV_2_wr = io_wr; // @[CacheRam.scala 36:30]
  assign ysyx_22051110_CacheMetaRamV_2_addr = {{1'd0}, io_index}; // @[CacheRam.scala 37:30]
  assign ysyx_22051110_CacheMetaRamV_2_wvalid = 1'h1; // @[CacheRam.scala 38:30]
  assign ysyx_22051110_CacheMetaRamV_2_wdirty = io_in_dirty; // @[CacheRam.scala 39:30]
  assign ysyx_22051110_CacheMetaRamV_2_wtag = io_in_tag; // @[CacheRam.scala 40:30]
  assign ysyx_22051110_CacheMetaRamV_3_clock = clock; // @[CacheRam.scala 32:30]
  assign ysyx_22051110_CacheMetaRamV_3_reset = reset; // @[CacheRam.scala 33:30]
  assign ysyx_22051110_CacheMetaRamV_3_flush = io_flush; // @[CacheRam.scala 34:30]
  assign ysyx_22051110_CacheMetaRamV_3_en = hit_array_3 & io_en; // @[CacheRam.scala 35:46]
  assign ysyx_22051110_CacheMetaRamV_3_wr = io_wr; // @[CacheRam.scala 36:30]
  assign ysyx_22051110_CacheMetaRamV_3_addr = {{1'd0}, io_index}; // @[CacheRam.scala 37:30]
  assign ysyx_22051110_CacheMetaRamV_3_wvalid = 1'h1; // @[CacheRam.scala 38:30]
  assign ysyx_22051110_CacheMetaRamV_3_wdirty = io_in_dirty; // @[CacheRam.scala 39:30]
  assign ysyx_22051110_CacheMetaRamV_3_wtag = io_in_tag; // @[CacheRam.scala 40:30]
endmodule
module ysyx_22051110_CacheTop(
  input          clock,
  input          reset,
  output         io_in_req_ready,
  input          io_in_req_valid,
  input  [31:0]  io_in_req_bits_addr,
  input          io_in_req_bits_mthrough,
  output [63:0]  io_in_ret_rdata,
  output         io_in_ret_valid,
  input          io_out_req_ready,
  output         io_out_req_valid,
  output         io_out_req_bits_wr,
  output [31:0]  io_out_req_bits_addr,
  output [1:0]   io_out_req_bits_size,
  output [127:0] io_out_req_bits_wdata,
  output [7:0]   io_out_req_bits_wstrb,
  output         io_out_req_bits_mthrough,
  input  [63:0]  io_out_ret_rdata,
  input          io_out_ret_valid,
  input          io_out_rlast,
  input          io_flush,
  output [5:0]   io_cache_data_0_addr,
  output         io_cache_data_0_cen,
  output         io_cache_data_0_wen,
  output [127:0] io_cache_data_0_wdata,
  input  [127:0] io_cache_data_0_rdata,
  output [5:0]   io_cache_data_1_addr,
  output         io_cache_data_1_cen,
  output         io_cache_data_1_wen,
  output [127:0] io_cache_data_1_wdata,
  input  [127:0] io_cache_data_1_rdata,
  output [5:0]   io_cache_data_2_addr,
  output         io_cache_data_2_cen,
  output         io_cache_data_2_wen,
  output [127:0] io_cache_data_2_wdata,
  input  [127:0] io_cache_data_2_rdata,
  output [5:0]   io_cache_data_3_addr,
  output         io_cache_data_3_cen,
  output         io_cache_data_3_wen,
  output [127:0] io_cache_data_3_wdata,
  input  [127:0] io_cache_data_3_rdata
);
  wire  stage1_io_cpu_ready; // @[CacheTop.scala 60:24]
  wire  stage1_io_cpu_valid; // @[CacheTop.scala 60:24]
  wire  stage1_io_cpu_bits_wr; // @[CacheTop.scala 60:24]
  wire [31:0] stage1_io_cpu_bits_addr; // @[CacheTop.scala 60:24]
  wire [1:0] stage1_io_cpu_bits_size; // @[CacheTop.scala 60:24]
  wire [63:0] stage1_io_cpu_bits_wdata; // @[CacheTop.scala 60:24]
  wire [7:0] stage1_io_cpu_bits_wstrb; // @[CacheTop.scala 60:24]
  wire  stage1_io_cpu_bits_mthrough; // @[CacheTop.scala 60:24]
  wire  stage1_io_cpu_bits_fencei; // @[CacheTop.scala 60:24]
  wire  stage1_io_rd_en; // @[CacheTop.scala 60:24]
  wire [4:0] stage1_io_rd_index; // @[CacheTop.scala 60:24]
  wire  stage1_io_s1_to_s2_ready; // @[CacheTop.scala 60:24]
  wire  stage1_io_s1_to_s2_valid; // @[CacheTop.scala 60:24]
  wire  stage1_io_s1_to_s2_bits_wr; // @[CacheTop.scala 60:24]
  wire [63:0] stage1_io_s1_to_s2_bits_wdata; // @[CacheTop.scala 60:24]
  wire [7:0] stage1_io_s1_to_s2_bits_wstrb; // @[CacheTop.scala 60:24]
  wire  stage1_io_s1_to_s2_bits_mthrough; // @[CacheTop.scala 60:24]
  wire [22:0] stage1_io_s1_to_s2_bits_tag; // @[CacheTop.scala 60:24]
  wire [4:0] stage1_io_s1_to_s2_bits_index; // @[CacheTop.scala 60:24]
  wire [3:0] stage1_io_s1_to_s2_bits_offset; // @[CacheTop.scala 60:24]
  wire [1:0] stage1_io_s1_to_s2_bits_size; // @[CacheTop.scala 60:24]
  wire  stage1_io_s1_to_s2_bits_fencei; // @[CacheTop.scala 60:24]
  wire  stage2_clock; // @[CacheTop.scala 61:24]
  wire  stage2_reset; // @[CacheTop.scala 61:24]
  wire  stage2_io_s1_to_s2_ready; // @[CacheTop.scala 61:24]
  wire  stage2_io_s1_to_s2_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_s1_to_s2_bits_wr; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_s1_to_s2_bits_wdata; // @[CacheTop.scala 61:24]
  wire [7:0] stage2_io_s1_to_s2_bits_wstrb; // @[CacheTop.scala 61:24]
  wire  stage2_io_s1_to_s2_bits_mthrough; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_s1_to_s2_bits_tag; // @[CacheTop.scala 61:24]
  wire [4:0] stage2_io_s1_to_s2_bits_index; // @[CacheTop.scala 61:24]
  wire [3:0] stage2_io_s1_to_s2_bits_offset; // @[CacheTop.scala 61:24]
  wire [1:0] stage2_io_s1_to_s2_bits_size; // @[CacheTop.scala 61:24]
  wire  stage2_io_s1_to_s2_bits_fencei; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_0_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_0_dirty; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_rd_lines_0_tag; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_0_data_0; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_0_data_1; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_1_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_1_dirty; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_rd_lines_1_tag; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_1_data_0; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_1_data_1; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_2_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_2_dirty; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_rd_lines_2_tag; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_2_data_0; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_2_data_1; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_3_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_3_dirty; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_rd_lines_3_tag; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_3_data_0; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_3_data_1; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_ready; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_bits_wr; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_s2_to_s3_bits_wdata; // @[CacheTop.scala 61:24]
  wire [7:0] stage2_io_s2_to_s3_bits_wstrb; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_bits_mthrough; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_s2_to_s3_bits_tag; // @[CacheTop.scala 61:24]
  wire [4:0] stage2_io_s2_to_s3_bits_index; // @[CacheTop.scala 61:24]
  wire [3:0] stage2_io_s2_to_s3_bits_offset; // @[CacheTop.scala 61:24]
  wire [1:0] stage2_io_s2_to_s3_bits_size; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_bits_hit; // @[CacheTop.scala 61:24]
  wire [1:0] stage2_io_s2_to_s3_bits_target_way; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_bits_target_line_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_bits_target_line_dirty; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_s2_to_s3_bits_target_line_tag; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_s2_to_s3_bits_target_line_data_0; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_s2_to_s3_bits_target_line_data_1; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_bits_fencei; // @[CacheTop.scala 61:24]
  wire  stage3_clock; // @[CacheTop.scala 62:24]
  wire  stage3_reset; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_cpu_rdata; // @[CacheTop.scala 62:24]
  wire  stage3_io_cpu_valid; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_ready; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_valid; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_bits_wr; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_s2_to_s3_bits_wdata; // @[CacheTop.scala 62:24]
  wire [7:0] stage3_io_s2_to_s3_bits_wstrb; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_bits_mthrough; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_s2_to_s3_bits_tag; // @[CacheTop.scala 62:24]
  wire [4:0] stage3_io_s2_to_s3_bits_index; // @[CacheTop.scala 62:24]
  wire [3:0] stage3_io_s2_to_s3_bits_offset; // @[CacheTop.scala 62:24]
  wire [1:0] stage3_io_s2_to_s3_bits_size; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_bits_hit; // @[CacheTop.scala 62:24]
  wire [1:0] stage3_io_s2_to_s3_bits_target_way; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_bits_target_line_valid; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_bits_target_line_dirty; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_s2_to_s3_bits_target_line_tag; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_s2_to_s3_bits_target_line_data_0; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_s2_to_s3_bits_target_line_data_1; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_bits_fencei; // @[CacheTop.scala 62:24]
  wire  stage3_io_wt_en; // @[CacheTop.scala 62:24]
  wire [1:0] stage3_io_wt_way; // @[CacheTop.scala 62:24]
  wire [4:0] stage3_io_wt_index; // @[CacheTop.scala 62:24]
  wire  stage3_io_wt_line_dirty; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_wt_line_tag; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_wt_line_data_0; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_wt_line_data_1; // @[CacheTop.scala 62:24]
  wire  stage3_io_mem_out_req_ready; // @[CacheTop.scala 62:24]
  wire  stage3_io_mem_out_req_valid; // @[CacheTop.scala 62:24]
  wire  stage3_io_mem_out_req_bits_wr; // @[CacheTop.scala 62:24]
  wire [31:0] stage3_io_mem_out_req_bits_addr; // @[CacheTop.scala 62:24]
  wire [1:0] stage3_io_mem_out_req_bits_size; // @[CacheTop.scala 62:24]
  wire [127:0] stage3_io_mem_out_req_bits_wdata; // @[CacheTop.scala 62:24]
  wire [7:0] stage3_io_mem_out_req_bits_wstrb; // @[CacheTop.scala 62:24]
  wire  stage3_io_mem_out_req_bits_mthrough; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_mem_out_ret_rdata; // @[CacheTop.scala 62:24]
  wire  stage3_io_mem_out_ret_valid; // @[CacheTop.scala 62:24]
  wire  stage3_io_mem_out_rlast; // @[CacheTop.scala 62:24]
  wire  stage3_io_meta_flush; // @[CacheTop.scala 62:24]
  wire  stage3_io_rd_en; // @[CacheTop.scala 62:24]
  wire [4:0] stage3_io_rd_index; // @[CacheTop.scala 62:24]
  wire  stage3_io_rd_lines_0_dirty; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_rd_lines_0_tag; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_0_data_0; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_0_data_1; // @[CacheTop.scala 62:24]
  wire  stage3_io_rd_lines_1_dirty; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_rd_lines_1_tag; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_1_data_0; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_1_data_1; // @[CacheTop.scala 62:24]
  wire  stage3_io_rd_lines_2_dirty; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_rd_lines_2_tag; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_2_data_0; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_2_data_1; // @[CacheTop.scala 62:24]
  wire  stage3_io_rd_lines_3_dirty; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_rd_lines_3_tag; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_3_data_0; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_3_data_1; // @[CacheTop.scala 62:24]
  wire  cache_meta_clock; // @[CacheTop.scala 84:28]
  wire  cache_meta_reset; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_flush; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_en; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_wr; // @[CacheTop.scala 84:28]
  wire [1:0] cache_meta_io_way; // @[CacheTop.scala 84:28]
  wire [4:0] cache_meta_io_index; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_0_valid; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_0_dirty; // @[CacheTop.scala 84:28]
  wire [22:0] cache_meta_io_out_0_tag; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_1_valid; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_1_dirty; // @[CacheTop.scala 84:28]
  wire [22:0] cache_meta_io_out_1_tag; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_2_valid; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_2_dirty; // @[CacheTop.scala 84:28]
  wire [22:0] cache_meta_io_out_2_tag; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_3_valid; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_3_dirty; // @[CacheTop.scala 84:28]
  wire [22:0] cache_meta_io_out_3_tag; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_in_dirty; // @[CacheTop.scala 84:28]
  wire [22:0] cache_meta_io_in_tag; // @[CacheTop.scala 84:28]
  wire [5:0] cache_wt_addr = {1'h0,stage3_io_wt_index}; // @[Cat.scala 33:92]
  wire [5:0] cache_rd_addr = {1'h0,stage1_io_rd_index}; // @[Cat.scala 33:92]
  wire [5:0] _cache_addr_T = stage3_io_wt_en ? cache_wt_addr : cache_rd_addr; // @[CacheTop.scala 82:69]
  wire [5:0] cache_addr = stage3_io_rd_en ? {{1'd0}, stage3_io_rd_index} : _cache_addr_T; // @[CacheTop.scala 82:28]
  ysyx_22051110_CacheStage1 stage1 ( // @[CacheTop.scala 60:24]
    .io_cpu_ready(stage1_io_cpu_ready),
    .io_cpu_valid(stage1_io_cpu_valid),
    .io_cpu_bits_wr(stage1_io_cpu_bits_wr),
    .io_cpu_bits_addr(stage1_io_cpu_bits_addr),
    .io_cpu_bits_size(stage1_io_cpu_bits_size),
    .io_cpu_bits_wdata(stage1_io_cpu_bits_wdata),
    .io_cpu_bits_wstrb(stage1_io_cpu_bits_wstrb),
    .io_cpu_bits_mthrough(stage1_io_cpu_bits_mthrough),
    .io_cpu_bits_fencei(stage1_io_cpu_bits_fencei),
    .io_rd_en(stage1_io_rd_en),
    .io_rd_index(stage1_io_rd_index),
    .io_s1_to_s2_ready(stage1_io_s1_to_s2_ready),
    .io_s1_to_s2_valid(stage1_io_s1_to_s2_valid),
    .io_s1_to_s2_bits_wr(stage1_io_s1_to_s2_bits_wr),
    .io_s1_to_s2_bits_wdata(stage1_io_s1_to_s2_bits_wdata),
    .io_s1_to_s2_bits_wstrb(stage1_io_s1_to_s2_bits_wstrb),
    .io_s1_to_s2_bits_mthrough(stage1_io_s1_to_s2_bits_mthrough),
    .io_s1_to_s2_bits_tag(stage1_io_s1_to_s2_bits_tag),
    .io_s1_to_s2_bits_index(stage1_io_s1_to_s2_bits_index),
    .io_s1_to_s2_bits_offset(stage1_io_s1_to_s2_bits_offset),
    .io_s1_to_s2_bits_size(stage1_io_s1_to_s2_bits_size),
    .io_s1_to_s2_bits_fencei(stage1_io_s1_to_s2_bits_fencei)
  );
  ysyx_22051110_CacheStage2 stage2 ( // @[CacheTop.scala 61:24]
    .clock(stage2_clock),
    .reset(stage2_reset),
    .io_s1_to_s2_ready(stage2_io_s1_to_s2_ready),
    .io_s1_to_s2_valid(stage2_io_s1_to_s2_valid),
    .io_s1_to_s2_bits_wr(stage2_io_s1_to_s2_bits_wr),
    .io_s1_to_s2_bits_wdata(stage2_io_s1_to_s2_bits_wdata),
    .io_s1_to_s2_bits_wstrb(stage2_io_s1_to_s2_bits_wstrb),
    .io_s1_to_s2_bits_mthrough(stage2_io_s1_to_s2_bits_mthrough),
    .io_s1_to_s2_bits_tag(stage2_io_s1_to_s2_bits_tag),
    .io_s1_to_s2_bits_index(stage2_io_s1_to_s2_bits_index),
    .io_s1_to_s2_bits_offset(stage2_io_s1_to_s2_bits_offset),
    .io_s1_to_s2_bits_size(stage2_io_s1_to_s2_bits_size),
    .io_s1_to_s2_bits_fencei(stage2_io_s1_to_s2_bits_fencei),
    .io_rd_lines_0_valid(stage2_io_rd_lines_0_valid),
    .io_rd_lines_0_dirty(stage2_io_rd_lines_0_dirty),
    .io_rd_lines_0_tag(stage2_io_rd_lines_0_tag),
    .io_rd_lines_0_data_0(stage2_io_rd_lines_0_data_0),
    .io_rd_lines_0_data_1(stage2_io_rd_lines_0_data_1),
    .io_rd_lines_1_valid(stage2_io_rd_lines_1_valid),
    .io_rd_lines_1_dirty(stage2_io_rd_lines_1_dirty),
    .io_rd_lines_1_tag(stage2_io_rd_lines_1_tag),
    .io_rd_lines_1_data_0(stage2_io_rd_lines_1_data_0),
    .io_rd_lines_1_data_1(stage2_io_rd_lines_1_data_1),
    .io_rd_lines_2_valid(stage2_io_rd_lines_2_valid),
    .io_rd_lines_2_dirty(stage2_io_rd_lines_2_dirty),
    .io_rd_lines_2_tag(stage2_io_rd_lines_2_tag),
    .io_rd_lines_2_data_0(stage2_io_rd_lines_2_data_0),
    .io_rd_lines_2_data_1(stage2_io_rd_lines_2_data_1),
    .io_rd_lines_3_valid(stage2_io_rd_lines_3_valid),
    .io_rd_lines_3_dirty(stage2_io_rd_lines_3_dirty),
    .io_rd_lines_3_tag(stage2_io_rd_lines_3_tag),
    .io_rd_lines_3_data_0(stage2_io_rd_lines_3_data_0),
    .io_rd_lines_3_data_1(stage2_io_rd_lines_3_data_1),
    .io_s2_to_s3_ready(stage2_io_s2_to_s3_ready),
    .io_s2_to_s3_valid(stage2_io_s2_to_s3_valid),
    .io_s2_to_s3_bits_wr(stage2_io_s2_to_s3_bits_wr),
    .io_s2_to_s3_bits_wdata(stage2_io_s2_to_s3_bits_wdata),
    .io_s2_to_s3_bits_wstrb(stage2_io_s2_to_s3_bits_wstrb),
    .io_s2_to_s3_bits_mthrough(stage2_io_s2_to_s3_bits_mthrough),
    .io_s2_to_s3_bits_tag(stage2_io_s2_to_s3_bits_tag),
    .io_s2_to_s3_bits_index(stage2_io_s2_to_s3_bits_index),
    .io_s2_to_s3_bits_offset(stage2_io_s2_to_s3_bits_offset),
    .io_s2_to_s3_bits_size(stage2_io_s2_to_s3_bits_size),
    .io_s2_to_s3_bits_hit(stage2_io_s2_to_s3_bits_hit),
    .io_s2_to_s3_bits_target_way(stage2_io_s2_to_s3_bits_target_way),
    .io_s2_to_s3_bits_target_line_valid(stage2_io_s2_to_s3_bits_target_line_valid),
    .io_s2_to_s3_bits_target_line_dirty(stage2_io_s2_to_s3_bits_target_line_dirty),
    .io_s2_to_s3_bits_target_line_tag(stage2_io_s2_to_s3_bits_target_line_tag),
    .io_s2_to_s3_bits_target_line_data_0(stage2_io_s2_to_s3_bits_target_line_data_0),
    .io_s2_to_s3_bits_target_line_data_1(stage2_io_s2_to_s3_bits_target_line_data_1),
    .io_s2_to_s3_bits_fencei(stage2_io_s2_to_s3_bits_fencei)
  );
  ysyx_22051110_CacheStage3 stage3 ( // @[CacheTop.scala 62:24]
    .clock(stage3_clock),
    .reset(stage3_reset),
    .io_cpu_rdata(stage3_io_cpu_rdata),
    .io_cpu_valid(stage3_io_cpu_valid),
    .io_s2_to_s3_ready(stage3_io_s2_to_s3_ready),
    .io_s2_to_s3_valid(stage3_io_s2_to_s3_valid),
    .io_s2_to_s3_bits_wr(stage3_io_s2_to_s3_bits_wr),
    .io_s2_to_s3_bits_wdata(stage3_io_s2_to_s3_bits_wdata),
    .io_s2_to_s3_bits_wstrb(stage3_io_s2_to_s3_bits_wstrb),
    .io_s2_to_s3_bits_mthrough(stage3_io_s2_to_s3_bits_mthrough),
    .io_s2_to_s3_bits_tag(stage3_io_s2_to_s3_bits_tag),
    .io_s2_to_s3_bits_index(stage3_io_s2_to_s3_bits_index),
    .io_s2_to_s3_bits_offset(stage3_io_s2_to_s3_bits_offset),
    .io_s2_to_s3_bits_size(stage3_io_s2_to_s3_bits_size),
    .io_s2_to_s3_bits_hit(stage3_io_s2_to_s3_bits_hit),
    .io_s2_to_s3_bits_target_way(stage3_io_s2_to_s3_bits_target_way),
    .io_s2_to_s3_bits_target_line_valid(stage3_io_s2_to_s3_bits_target_line_valid),
    .io_s2_to_s3_bits_target_line_dirty(stage3_io_s2_to_s3_bits_target_line_dirty),
    .io_s2_to_s3_bits_target_line_tag(stage3_io_s2_to_s3_bits_target_line_tag),
    .io_s2_to_s3_bits_target_line_data_0(stage3_io_s2_to_s3_bits_target_line_data_0),
    .io_s2_to_s3_bits_target_line_data_1(stage3_io_s2_to_s3_bits_target_line_data_1),
    .io_s2_to_s3_bits_fencei(stage3_io_s2_to_s3_bits_fencei),
    .io_wt_en(stage3_io_wt_en),
    .io_wt_way(stage3_io_wt_way),
    .io_wt_index(stage3_io_wt_index),
    .io_wt_line_dirty(stage3_io_wt_line_dirty),
    .io_wt_line_tag(stage3_io_wt_line_tag),
    .io_wt_line_data_0(stage3_io_wt_line_data_0),
    .io_wt_line_data_1(stage3_io_wt_line_data_1),
    .io_mem_out_req_ready(stage3_io_mem_out_req_ready),
    .io_mem_out_req_valid(stage3_io_mem_out_req_valid),
    .io_mem_out_req_bits_wr(stage3_io_mem_out_req_bits_wr),
    .io_mem_out_req_bits_addr(stage3_io_mem_out_req_bits_addr),
    .io_mem_out_req_bits_size(stage3_io_mem_out_req_bits_size),
    .io_mem_out_req_bits_wdata(stage3_io_mem_out_req_bits_wdata),
    .io_mem_out_req_bits_wstrb(stage3_io_mem_out_req_bits_wstrb),
    .io_mem_out_req_bits_mthrough(stage3_io_mem_out_req_bits_mthrough),
    .io_mem_out_ret_rdata(stage3_io_mem_out_ret_rdata),
    .io_mem_out_ret_valid(stage3_io_mem_out_ret_valid),
    .io_mem_out_rlast(stage3_io_mem_out_rlast),
    .io_meta_flush(stage3_io_meta_flush),
    .io_rd_en(stage3_io_rd_en),
    .io_rd_index(stage3_io_rd_index),
    .io_rd_lines_0_dirty(stage3_io_rd_lines_0_dirty),
    .io_rd_lines_0_tag(stage3_io_rd_lines_0_tag),
    .io_rd_lines_0_data_0(stage3_io_rd_lines_0_data_0),
    .io_rd_lines_0_data_1(stage3_io_rd_lines_0_data_1),
    .io_rd_lines_1_dirty(stage3_io_rd_lines_1_dirty),
    .io_rd_lines_1_tag(stage3_io_rd_lines_1_tag),
    .io_rd_lines_1_data_0(stage3_io_rd_lines_1_data_0),
    .io_rd_lines_1_data_1(stage3_io_rd_lines_1_data_1),
    .io_rd_lines_2_dirty(stage3_io_rd_lines_2_dirty),
    .io_rd_lines_2_tag(stage3_io_rd_lines_2_tag),
    .io_rd_lines_2_data_0(stage3_io_rd_lines_2_data_0),
    .io_rd_lines_2_data_1(stage3_io_rd_lines_2_data_1),
    .io_rd_lines_3_dirty(stage3_io_rd_lines_3_dirty),
    .io_rd_lines_3_tag(stage3_io_rd_lines_3_tag),
    .io_rd_lines_3_data_0(stage3_io_rd_lines_3_data_0),
    .io_rd_lines_3_data_1(stage3_io_rd_lines_3_data_1)
  );
  ysyx_22051110_CacheMetaRam cache_meta ( // @[CacheTop.scala 84:28]
    .clock(cache_meta_clock),
    .reset(cache_meta_reset),
    .io_flush(cache_meta_io_flush),
    .io_en(cache_meta_io_en),
    .io_wr(cache_meta_io_wr),
    .io_way(cache_meta_io_way),
    .io_index(cache_meta_io_index),
    .io_out_0_valid(cache_meta_io_out_0_valid),
    .io_out_0_dirty(cache_meta_io_out_0_dirty),
    .io_out_0_tag(cache_meta_io_out_0_tag),
    .io_out_1_valid(cache_meta_io_out_1_valid),
    .io_out_1_dirty(cache_meta_io_out_1_dirty),
    .io_out_1_tag(cache_meta_io_out_1_tag),
    .io_out_2_valid(cache_meta_io_out_2_valid),
    .io_out_2_dirty(cache_meta_io_out_2_dirty),
    .io_out_2_tag(cache_meta_io_out_2_tag),
    .io_out_3_valid(cache_meta_io_out_3_valid),
    .io_out_3_dirty(cache_meta_io_out_3_dirty),
    .io_out_3_tag(cache_meta_io_out_3_tag),
    .io_in_dirty(cache_meta_io_in_dirty),
    .io_in_tag(cache_meta_io_in_tag)
  );
  assign io_in_req_ready = stage1_io_cpu_ready; // @[CacheTop.scala 126:19]
  assign io_in_ret_rdata = stage3_io_cpu_rdata; // @[CacheTop.scala 127:19]
  assign io_in_ret_valid = stage3_io_cpu_valid; // @[CacheTop.scala 127:19]
  assign io_out_req_valid = stage3_io_mem_out_req_valid; // @[CacheTop.scala 129:12]
  assign io_out_req_bits_wr = stage3_io_mem_out_req_bits_wr; // @[CacheTop.scala 129:12]
  assign io_out_req_bits_addr = stage3_io_mem_out_req_bits_addr; // @[CacheTop.scala 129:12]
  assign io_out_req_bits_size = stage3_io_mem_out_req_bits_size; // @[CacheTop.scala 129:12]
  assign io_out_req_bits_wdata = stage3_io_mem_out_req_bits_wdata; // @[CacheTop.scala 129:12]
  assign io_out_req_bits_wstrb = stage3_io_mem_out_req_bits_wstrb; // @[CacheTop.scala 129:12]
  assign io_out_req_bits_mthrough = stage3_io_mem_out_req_bits_mthrough; // @[CacheTop.scala 129:12]
  assign io_cache_data_0_addr = stage3_io_rd_en ? {{1'd0}, stage3_io_rd_index} : _cache_addr_T; // @[CacheTop.scala 82:28]
  assign io_cache_data_0_cen = ~(stage1_io_rd_en | stage3_io_rd_en | stage3_io_wt_en); // @[CacheTop.scala 100:35]
  assign io_cache_data_0_wen = ~(stage3_io_wt_en & stage3_io_wt_way == 2'h0); // @[CacheTop.scala 101:35]
  assign io_cache_data_0_wdata = {stage3_io_wt_line_data_1,stage3_io_wt_line_data_0}; // @[Cat.scala 33:92]
  assign io_cache_data_1_addr = stage3_io_rd_en ? {{1'd0}, stage3_io_rd_index} : _cache_addr_T; // @[CacheTop.scala 82:28]
  assign io_cache_data_1_cen = ~(stage1_io_rd_en | stage3_io_rd_en | stage3_io_wt_en); // @[CacheTop.scala 100:35]
  assign io_cache_data_1_wen = ~(stage3_io_wt_en & stage3_io_wt_way == 2'h1); // @[CacheTop.scala 101:35]
  assign io_cache_data_1_wdata = {stage3_io_wt_line_data_1,stage3_io_wt_line_data_0}; // @[Cat.scala 33:92]
  assign io_cache_data_2_addr = stage3_io_rd_en ? {{1'd0}, stage3_io_rd_index} : _cache_addr_T; // @[CacheTop.scala 82:28]
  assign io_cache_data_2_cen = ~(stage1_io_rd_en | stage3_io_rd_en | stage3_io_wt_en); // @[CacheTop.scala 100:35]
  assign io_cache_data_2_wen = ~(stage3_io_wt_en & stage3_io_wt_way == 2'h2); // @[CacheTop.scala 101:35]
  assign io_cache_data_2_wdata = {stage3_io_wt_line_data_1,stage3_io_wt_line_data_0}; // @[Cat.scala 33:92]
  assign io_cache_data_3_addr = stage3_io_rd_en ? {{1'd0}, stage3_io_rd_index} : _cache_addr_T; // @[CacheTop.scala 82:28]
  assign io_cache_data_3_cen = ~(stage1_io_rd_en | stage3_io_rd_en | stage3_io_wt_en); // @[CacheTop.scala 100:35]
  assign io_cache_data_3_wen = ~(stage3_io_wt_en & stage3_io_wt_way == 2'h3); // @[CacheTop.scala 101:35]
  assign io_cache_data_3_wdata = {stage3_io_wt_line_data_1,stage3_io_wt_line_data_0}; // @[Cat.scala 33:92]
  assign stage1_io_cpu_valid = io_in_req_valid; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_wr = 1'h0; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_addr = io_in_req_bits_addr; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_size = 2'h2; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_wdata = 64'h0; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_wstrb = 8'h0; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_mthrough = io_in_req_bits_mthrough; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_fencei = 1'h0; // @[CacheTop.scala 126:19]
  assign stage1_io_s1_to_s2_ready = stage2_io_s1_to_s2_ready; // @[CacheTop.scala 123:24]
  assign stage2_clock = clock;
  assign stage2_reset = reset;
  assign stage2_io_s1_to_s2_valid = stage1_io_s1_to_s2_valid; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_wr = stage1_io_s1_to_s2_bits_wr; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_wdata = stage1_io_s1_to_s2_bits_wdata; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_wstrb = stage1_io_s1_to_s2_bits_wstrb; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_mthrough = stage1_io_s1_to_s2_bits_mthrough; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_tag = stage1_io_s1_to_s2_bits_tag; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_index = stage1_io_s1_to_s2_bits_index; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_offset = stage1_io_s1_to_s2_bits_offset; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_size = stage1_io_s1_to_s2_bits_size; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_fencei = stage1_io_s1_to_s2_bits_fencei; // @[CacheTop.scala 123:24]
  assign stage2_io_rd_lines_0_valid = cache_meta_io_out_0_valid; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_0_dirty = cache_meta_io_out_0_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_0_tag = cache_meta_io_out_0_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_0_data_0 = io_cache_data_0_rdata[63:0]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_0_data_1 = io_cache_data_0_rdata[127:64]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_1_valid = cache_meta_io_out_1_valid; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_1_dirty = cache_meta_io_out_1_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_1_tag = cache_meta_io_out_1_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_1_data_0 = io_cache_data_1_rdata[63:0]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_1_data_1 = io_cache_data_1_rdata[127:64]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_2_valid = cache_meta_io_out_2_valid; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_2_dirty = cache_meta_io_out_2_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_2_tag = cache_meta_io_out_2_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_2_data_0 = io_cache_data_2_rdata[63:0]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_2_data_1 = io_cache_data_2_rdata[127:64]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_3_valid = cache_meta_io_out_3_valid; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_3_dirty = cache_meta_io_out_3_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_3_tag = cache_meta_io_out_3_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_3_data_0 = io_cache_data_3_rdata[63:0]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_3_data_1 = io_cache_data_3_rdata[127:64]; // @[CacheTop.scala 116:61]
  assign stage2_io_s2_to_s3_ready = stage3_io_s2_to_s3_ready; // @[CacheTop.scala 124:24]
  assign stage3_clock = clock;
  assign stage3_reset = reset;
  assign stage3_io_s2_to_s3_valid = stage2_io_s2_to_s3_valid; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_wr = stage2_io_s2_to_s3_bits_wr; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_wdata = stage2_io_s2_to_s3_bits_wdata; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_wstrb = stage2_io_s2_to_s3_bits_wstrb; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_mthrough = stage2_io_s2_to_s3_bits_mthrough; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_tag = stage2_io_s2_to_s3_bits_tag; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_index = stage2_io_s2_to_s3_bits_index; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_offset = stage2_io_s2_to_s3_bits_offset; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_size = stage2_io_s2_to_s3_bits_size; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_hit = stage2_io_s2_to_s3_bits_hit; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_target_way = stage2_io_s2_to_s3_bits_target_way; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_target_line_valid = stage2_io_s2_to_s3_bits_target_line_valid; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_target_line_dirty = stage2_io_s2_to_s3_bits_target_line_dirty; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_target_line_tag = stage2_io_s2_to_s3_bits_target_line_tag; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_target_line_data_0 = stage2_io_s2_to_s3_bits_target_line_data_0; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_target_line_data_1 = stage2_io_s2_to_s3_bits_target_line_data_1; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_fencei = stage2_io_s2_to_s3_bits_fencei; // @[CacheTop.scala 124:24]
  assign stage3_io_mem_out_req_ready = io_out_req_ready; // @[CacheTop.scala 129:12]
  assign stage3_io_mem_out_ret_rdata = io_out_ret_rdata; // @[CacheTop.scala 129:12]
  assign stage3_io_mem_out_ret_valid = io_out_ret_valid; // @[CacheTop.scala 129:12]
  assign stage3_io_mem_out_rlast = io_out_rlast; // @[CacheTop.scala 129:12]
  assign stage3_io_rd_lines_0_dirty = cache_meta_io_out_0_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_0_tag = cache_meta_io_out_0_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_0_data_0 = io_cache_data_0_rdata[63:0]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_0_data_1 = io_cache_data_0_rdata[127:64]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_1_dirty = cache_meta_io_out_1_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_1_tag = cache_meta_io_out_1_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_1_data_0 = io_cache_data_1_rdata[63:0]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_1_data_1 = io_cache_data_1_rdata[127:64]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_2_dirty = cache_meta_io_out_2_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_2_tag = cache_meta_io_out_2_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_2_data_0 = io_cache_data_2_rdata[63:0]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_2_data_1 = io_cache_data_2_rdata[127:64]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_3_dirty = cache_meta_io_out_3_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_3_tag = cache_meta_io_out_3_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_3_data_0 = io_cache_data_3_rdata[63:0]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_3_data_1 = io_cache_data_3_rdata[127:64]; // @[CacheTop.scala 117:61]
  assign cache_meta_clock = clock;
  assign cache_meta_reset = reset;
  assign cache_meta_io_flush = io_flush; // @[CacheTop.scala 87:25]
  assign cache_meta_io_en = stage1_io_rd_en | stage3_io_wt_en | stage3_io_rd_en; // @[CacheTop.scala 88:63]
  assign cache_meta_io_wr = stage3_io_wt_en; // @[CacheTop.scala 89:25]
  assign cache_meta_io_way = stage3_io_wt_way; // @[CacheTop.scala 90:25]
  assign cache_meta_io_index = cache_addr[4:0]; // @[CacheTop.scala 91:25]
  assign cache_meta_io_in_dirty = stage3_io_wt_line_dirty; // @[CacheTop.scala 94:28]
  assign cache_meta_io_in_tag = stage3_io_wt_line_tag; // @[CacheTop.scala 95:28]
endmodule
module ysyx_22051110_CacheTop_1(
  input          clock,
  input          reset,
  output         io_in_req_ready,
  input          io_in_req_valid,
  input          io_in_req_bits_wr,
  input  [31:0]  io_in_req_bits_addr,
  input  [1:0]   io_in_req_bits_size,
  input  [63:0]  io_in_req_bits_wdata,
  input  [7:0]   io_in_req_bits_wstrb,
  input          io_in_req_bits_mthrough,
  input          io_in_req_bits_fencei,
  output [63:0]  io_in_ret_rdata,
  output         io_in_ret_valid,
  input          io_out_req_ready,
  output         io_out_req_valid,
  output         io_out_req_bits_wr,
  output [31:0]  io_out_req_bits_addr,
  output [1:0]   io_out_req_bits_size,
  output [127:0] io_out_req_bits_wdata,
  output [7:0]   io_out_req_bits_wstrb,
  output         io_out_req_bits_mthrough,
  input  [63:0]  io_out_ret_rdata,
  input          io_out_ret_valid,
  input          io_out_rlast,
  output         io_flush,
  output [5:0]   io_cache_data_0_addr,
  output         io_cache_data_0_cen,
  output         io_cache_data_0_wen,
  output [127:0] io_cache_data_0_wdata,
  input  [127:0] io_cache_data_0_rdata,
  output [5:0]   io_cache_data_1_addr,
  output         io_cache_data_1_cen,
  output         io_cache_data_1_wen,
  output [127:0] io_cache_data_1_wdata,
  input  [127:0] io_cache_data_1_rdata,
  output [5:0]   io_cache_data_2_addr,
  output         io_cache_data_2_cen,
  output         io_cache_data_2_wen,
  output [127:0] io_cache_data_2_wdata,
  input  [127:0] io_cache_data_2_rdata,
  output [5:0]   io_cache_data_3_addr,
  output         io_cache_data_3_cen,
  output         io_cache_data_3_wen,
  output [127:0] io_cache_data_3_wdata,
  input  [127:0] io_cache_data_3_rdata
);
  wire  stage1_io_cpu_ready; // @[CacheTop.scala 60:24]
  wire  stage1_io_cpu_valid; // @[CacheTop.scala 60:24]
  wire  stage1_io_cpu_bits_wr; // @[CacheTop.scala 60:24]
  wire [31:0] stage1_io_cpu_bits_addr; // @[CacheTop.scala 60:24]
  wire [1:0] stage1_io_cpu_bits_size; // @[CacheTop.scala 60:24]
  wire [63:0] stage1_io_cpu_bits_wdata; // @[CacheTop.scala 60:24]
  wire [7:0] stage1_io_cpu_bits_wstrb; // @[CacheTop.scala 60:24]
  wire  stage1_io_cpu_bits_mthrough; // @[CacheTop.scala 60:24]
  wire  stage1_io_cpu_bits_fencei; // @[CacheTop.scala 60:24]
  wire  stage1_io_rd_en; // @[CacheTop.scala 60:24]
  wire [4:0] stage1_io_rd_index; // @[CacheTop.scala 60:24]
  wire  stage1_io_s1_to_s2_ready; // @[CacheTop.scala 60:24]
  wire  stage1_io_s1_to_s2_valid; // @[CacheTop.scala 60:24]
  wire  stage1_io_s1_to_s2_bits_wr; // @[CacheTop.scala 60:24]
  wire [63:0] stage1_io_s1_to_s2_bits_wdata; // @[CacheTop.scala 60:24]
  wire [7:0] stage1_io_s1_to_s2_bits_wstrb; // @[CacheTop.scala 60:24]
  wire  stage1_io_s1_to_s2_bits_mthrough; // @[CacheTop.scala 60:24]
  wire [22:0] stage1_io_s1_to_s2_bits_tag; // @[CacheTop.scala 60:24]
  wire [4:0] stage1_io_s1_to_s2_bits_index; // @[CacheTop.scala 60:24]
  wire [3:0] stage1_io_s1_to_s2_bits_offset; // @[CacheTop.scala 60:24]
  wire [1:0] stage1_io_s1_to_s2_bits_size; // @[CacheTop.scala 60:24]
  wire  stage1_io_s1_to_s2_bits_fencei; // @[CacheTop.scala 60:24]
  wire  stage2_clock; // @[CacheTop.scala 61:24]
  wire  stage2_reset; // @[CacheTop.scala 61:24]
  wire  stage2_io_s1_to_s2_ready; // @[CacheTop.scala 61:24]
  wire  stage2_io_s1_to_s2_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_s1_to_s2_bits_wr; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_s1_to_s2_bits_wdata; // @[CacheTop.scala 61:24]
  wire [7:0] stage2_io_s1_to_s2_bits_wstrb; // @[CacheTop.scala 61:24]
  wire  stage2_io_s1_to_s2_bits_mthrough; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_s1_to_s2_bits_tag; // @[CacheTop.scala 61:24]
  wire [4:0] stage2_io_s1_to_s2_bits_index; // @[CacheTop.scala 61:24]
  wire [3:0] stage2_io_s1_to_s2_bits_offset; // @[CacheTop.scala 61:24]
  wire [1:0] stage2_io_s1_to_s2_bits_size; // @[CacheTop.scala 61:24]
  wire  stage2_io_s1_to_s2_bits_fencei; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_0_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_0_dirty; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_rd_lines_0_tag; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_0_data_0; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_0_data_1; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_1_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_1_dirty; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_rd_lines_1_tag; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_1_data_0; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_1_data_1; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_2_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_2_dirty; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_rd_lines_2_tag; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_2_data_0; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_2_data_1; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_3_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_rd_lines_3_dirty; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_rd_lines_3_tag; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_3_data_0; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_rd_lines_3_data_1; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_ready; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_bits_wr; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_s2_to_s3_bits_wdata; // @[CacheTop.scala 61:24]
  wire [7:0] stage2_io_s2_to_s3_bits_wstrb; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_bits_mthrough; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_s2_to_s3_bits_tag; // @[CacheTop.scala 61:24]
  wire [4:0] stage2_io_s2_to_s3_bits_index; // @[CacheTop.scala 61:24]
  wire [3:0] stage2_io_s2_to_s3_bits_offset; // @[CacheTop.scala 61:24]
  wire [1:0] stage2_io_s2_to_s3_bits_size; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_bits_hit; // @[CacheTop.scala 61:24]
  wire [1:0] stage2_io_s2_to_s3_bits_target_way; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_bits_target_line_valid; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_bits_target_line_dirty; // @[CacheTop.scala 61:24]
  wire [22:0] stage2_io_s2_to_s3_bits_target_line_tag; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_s2_to_s3_bits_target_line_data_0; // @[CacheTop.scala 61:24]
  wire [63:0] stage2_io_s2_to_s3_bits_target_line_data_1; // @[CacheTop.scala 61:24]
  wire  stage2_io_s2_to_s3_bits_fencei; // @[CacheTop.scala 61:24]
  wire  stage3_clock; // @[CacheTop.scala 62:24]
  wire  stage3_reset; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_cpu_rdata; // @[CacheTop.scala 62:24]
  wire  stage3_io_cpu_valid; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_ready; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_valid; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_bits_wr; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_s2_to_s3_bits_wdata; // @[CacheTop.scala 62:24]
  wire [7:0] stage3_io_s2_to_s3_bits_wstrb; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_bits_mthrough; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_s2_to_s3_bits_tag; // @[CacheTop.scala 62:24]
  wire [4:0] stage3_io_s2_to_s3_bits_index; // @[CacheTop.scala 62:24]
  wire [3:0] stage3_io_s2_to_s3_bits_offset; // @[CacheTop.scala 62:24]
  wire [1:0] stage3_io_s2_to_s3_bits_size; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_bits_hit; // @[CacheTop.scala 62:24]
  wire [1:0] stage3_io_s2_to_s3_bits_target_way; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_bits_target_line_valid; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_bits_target_line_dirty; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_s2_to_s3_bits_target_line_tag; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_s2_to_s3_bits_target_line_data_0; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_s2_to_s3_bits_target_line_data_1; // @[CacheTop.scala 62:24]
  wire  stage3_io_s2_to_s3_bits_fencei; // @[CacheTop.scala 62:24]
  wire  stage3_io_wt_en; // @[CacheTop.scala 62:24]
  wire [1:0] stage3_io_wt_way; // @[CacheTop.scala 62:24]
  wire [4:0] stage3_io_wt_index; // @[CacheTop.scala 62:24]
  wire  stage3_io_wt_line_dirty; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_wt_line_tag; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_wt_line_data_0; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_wt_line_data_1; // @[CacheTop.scala 62:24]
  wire  stage3_io_mem_out_req_ready; // @[CacheTop.scala 62:24]
  wire  stage3_io_mem_out_req_valid; // @[CacheTop.scala 62:24]
  wire  stage3_io_mem_out_req_bits_wr; // @[CacheTop.scala 62:24]
  wire [31:0] stage3_io_mem_out_req_bits_addr; // @[CacheTop.scala 62:24]
  wire [1:0] stage3_io_mem_out_req_bits_size; // @[CacheTop.scala 62:24]
  wire [127:0] stage3_io_mem_out_req_bits_wdata; // @[CacheTop.scala 62:24]
  wire [7:0] stage3_io_mem_out_req_bits_wstrb; // @[CacheTop.scala 62:24]
  wire  stage3_io_mem_out_req_bits_mthrough; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_mem_out_ret_rdata; // @[CacheTop.scala 62:24]
  wire  stage3_io_mem_out_ret_valid; // @[CacheTop.scala 62:24]
  wire  stage3_io_mem_out_rlast; // @[CacheTop.scala 62:24]
  wire  stage3_io_meta_flush; // @[CacheTop.scala 62:24]
  wire  stage3_io_rd_en; // @[CacheTop.scala 62:24]
  wire [4:0] stage3_io_rd_index; // @[CacheTop.scala 62:24]
  wire  stage3_io_rd_lines_0_dirty; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_rd_lines_0_tag; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_0_data_0; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_0_data_1; // @[CacheTop.scala 62:24]
  wire  stage3_io_rd_lines_1_dirty; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_rd_lines_1_tag; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_1_data_0; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_1_data_1; // @[CacheTop.scala 62:24]
  wire  stage3_io_rd_lines_2_dirty; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_rd_lines_2_tag; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_2_data_0; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_2_data_1; // @[CacheTop.scala 62:24]
  wire  stage3_io_rd_lines_3_dirty; // @[CacheTop.scala 62:24]
  wire [22:0] stage3_io_rd_lines_3_tag; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_3_data_0; // @[CacheTop.scala 62:24]
  wire [63:0] stage3_io_rd_lines_3_data_1; // @[CacheTop.scala 62:24]
  wire  cache_meta_clock; // @[CacheTop.scala 84:28]
  wire  cache_meta_reset; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_flush; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_en; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_wr; // @[CacheTop.scala 84:28]
  wire [1:0] cache_meta_io_way; // @[CacheTop.scala 84:28]
  wire [4:0] cache_meta_io_index; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_0_valid; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_0_dirty; // @[CacheTop.scala 84:28]
  wire [22:0] cache_meta_io_out_0_tag; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_1_valid; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_1_dirty; // @[CacheTop.scala 84:28]
  wire [22:0] cache_meta_io_out_1_tag; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_2_valid; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_2_dirty; // @[CacheTop.scala 84:28]
  wire [22:0] cache_meta_io_out_2_tag; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_3_valid; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_out_3_dirty; // @[CacheTop.scala 84:28]
  wire [22:0] cache_meta_io_out_3_tag; // @[CacheTop.scala 84:28]
  wire  cache_meta_io_in_dirty; // @[CacheTop.scala 84:28]
  wire [22:0] cache_meta_io_in_tag; // @[CacheTop.scala 84:28]
  wire [5:0] cache_wt_addr = {1'h0,stage3_io_wt_index}; // @[Cat.scala 33:92]
  wire [5:0] cache_rd_addr = {1'h0,stage1_io_rd_index}; // @[Cat.scala 33:92]
  wire [5:0] _cache_addr_T = stage3_io_wt_en ? cache_wt_addr : cache_rd_addr; // @[CacheTop.scala 82:69]
  wire [5:0] cache_addr = stage3_io_rd_en ? {{1'd0}, stage3_io_rd_index} : _cache_addr_T; // @[CacheTop.scala 82:28]
  ysyx_22051110_CacheStage1 stage1 ( // @[CacheTop.scala 60:24]
    .io_cpu_ready(stage1_io_cpu_ready),
    .io_cpu_valid(stage1_io_cpu_valid),
    .io_cpu_bits_wr(stage1_io_cpu_bits_wr),
    .io_cpu_bits_addr(stage1_io_cpu_bits_addr),
    .io_cpu_bits_size(stage1_io_cpu_bits_size),
    .io_cpu_bits_wdata(stage1_io_cpu_bits_wdata),
    .io_cpu_bits_wstrb(stage1_io_cpu_bits_wstrb),
    .io_cpu_bits_mthrough(stage1_io_cpu_bits_mthrough),
    .io_cpu_bits_fencei(stage1_io_cpu_bits_fencei),
    .io_rd_en(stage1_io_rd_en),
    .io_rd_index(stage1_io_rd_index),
    .io_s1_to_s2_ready(stage1_io_s1_to_s2_ready),
    .io_s1_to_s2_valid(stage1_io_s1_to_s2_valid),
    .io_s1_to_s2_bits_wr(stage1_io_s1_to_s2_bits_wr),
    .io_s1_to_s2_bits_wdata(stage1_io_s1_to_s2_bits_wdata),
    .io_s1_to_s2_bits_wstrb(stage1_io_s1_to_s2_bits_wstrb),
    .io_s1_to_s2_bits_mthrough(stage1_io_s1_to_s2_bits_mthrough),
    .io_s1_to_s2_bits_tag(stage1_io_s1_to_s2_bits_tag),
    .io_s1_to_s2_bits_index(stage1_io_s1_to_s2_bits_index),
    .io_s1_to_s2_bits_offset(stage1_io_s1_to_s2_bits_offset),
    .io_s1_to_s2_bits_size(stage1_io_s1_to_s2_bits_size),
    .io_s1_to_s2_bits_fencei(stage1_io_s1_to_s2_bits_fencei)
  );
  ysyx_22051110_CacheStage2 stage2 ( // @[CacheTop.scala 61:24]
    .clock(stage2_clock),
    .reset(stage2_reset),
    .io_s1_to_s2_ready(stage2_io_s1_to_s2_ready),
    .io_s1_to_s2_valid(stage2_io_s1_to_s2_valid),
    .io_s1_to_s2_bits_wr(stage2_io_s1_to_s2_bits_wr),
    .io_s1_to_s2_bits_wdata(stage2_io_s1_to_s2_bits_wdata),
    .io_s1_to_s2_bits_wstrb(stage2_io_s1_to_s2_bits_wstrb),
    .io_s1_to_s2_bits_mthrough(stage2_io_s1_to_s2_bits_mthrough),
    .io_s1_to_s2_bits_tag(stage2_io_s1_to_s2_bits_tag),
    .io_s1_to_s2_bits_index(stage2_io_s1_to_s2_bits_index),
    .io_s1_to_s2_bits_offset(stage2_io_s1_to_s2_bits_offset),
    .io_s1_to_s2_bits_size(stage2_io_s1_to_s2_bits_size),
    .io_s1_to_s2_bits_fencei(stage2_io_s1_to_s2_bits_fencei),
    .io_rd_lines_0_valid(stage2_io_rd_lines_0_valid),
    .io_rd_lines_0_dirty(stage2_io_rd_lines_0_dirty),
    .io_rd_lines_0_tag(stage2_io_rd_lines_0_tag),
    .io_rd_lines_0_data_0(stage2_io_rd_lines_0_data_0),
    .io_rd_lines_0_data_1(stage2_io_rd_lines_0_data_1),
    .io_rd_lines_1_valid(stage2_io_rd_lines_1_valid),
    .io_rd_lines_1_dirty(stage2_io_rd_lines_1_dirty),
    .io_rd_lines_1_tag(stage2_io_rd_lines_1_tag),
    .io_rd_lines_1_data_0(stage2_io_rd_lines_1_data_0),
    .io_rd_lines_1_data_1(stage2_io_rd_lines_1_data_1),
    .io_rd_lines_2_valid(stage2_io_rd_lines_2_valid),
    .io_rd_lines_2_dirty(stage2_io_rd_lines_2_dirty),
    .io_rd_lines_2_tag(stage2_io_rd_lines_2_tag),
    .io_rd_lines_2_data_0(stage2_io_rd_lines_2_data_0),
    .io_rd_lines_2_data_1(stage2_io_rd_lines_2_data_1),
    .io_rd_lines_3_valid(stage2_io_rd_lines_3_valid),
    .io_rd_lines_3_dirty(stage2_io_rd_lines_3_dirty),
    .io_rd_lines_3_tag(stage2_io_rd_lines_3_tag),
    .io_rd_lines_3_data_0(stage2_io_rd_lines_3_data_0),
    .io_rd_lines_3_data_1(stage2_io_rd_lines_3_data_1),
    .io_s2_to_s3_ready(stage2_io_s2_to_s3_ready),
    .io_s2_to_s3_valid(stage2_io_s2_to_s3_valid),
    .io_s2_to_s3_bits_wr(stage2_io_s2_to_s3_bits_wr),
    .io_s2_to_s3_bits_wdata(stage2_io_s2_to_s3_bits_wdata),
    .io_s2_to_s3_bits_wstrb(stage2_io_s2_to_s3_bits_wstrb),
    .io_s2_to_s3_bits_mthrough(stage2_io_s2_to_s3_bits_mthrough),
    .io_s2_to_s3_bits_tag(stage2_io_s2_to_s3_bits_tag),
    .io_s2_to_s3_bits_index(stage2_io_s2_to_s3_bits_index),
    .io_s2_to_s3_bits_offset(stage2_io_s2_to_s3_bits_offset),
    .io_s2_to_s3_bits_size(stage2_io_s2_to_s3_bits_size),
    .io_s2_to_s3_bits_hit(stage2_io_s2_to_s3_bits_hit),
    .io_s2_to_s3_bits_target_way(stage2_io_s2_to_s3_bits_target_way),
    .io_s2_to_s3_bits_target_line_valid(stage2_io_s2_to_s3_bits_target_line_valid),
    .io_s2_to_s3_bits_target_line_dirty(stage2_io_s2_to_s3_bits_target_line_dirty),
    .io_s2_to_s3_bits_target_line_tag(stage2_io_s2_to_s3_bits_target_line_tag),
    .io_s2_to_s3_bits_target_line_data_0(stage2_io_s2_to_s3_bits_target_line_data_0),
    .io_s2_to_s3_bits_target_line_data_1(stage2_io_s2_to_s3_bits_target_line_data_1),
    .io_s2_to_s3_bits_fencei(stage2_io_s2_to_s3_bits_fencei)
  );
  ysyx_22051110_CacheStage3 stage3 ( // @[CacheTop.scala 62:24]
    .clock(stage3_clock),
    .reset(stage3_reset),
    .io_cpu_rdata(stage3_io_cpu_rdata),
    .io_cpu_valid(stage3_io_cpu_valid),
    .io_s2_to_s3_ready(stage3_io_s2_to_s3_ready),
    .io_s2_to_s3_valid(stage3_io_s2_to_s3_valid),
    .io_s2_to_s3_bits_wr(stage3_io_s2_to_s3_bits_wr),
    .io_s2_to_s3_bits_wdata(stage3_io_s2_to_s3_bits_wdata),
    .io_s2_to_s3_bits_wstrb(stage3_io_s2_to_s3_bits_wstrb),
    .io_s2_to_s3_bits_mthrough(stage3_io_s2_to_s3_bits_mthrough),
    .io_s2_to_s3_bits_tag(stage3_io_s2_to_s3_bits_tag),
    .io_s2_to_s3_bits_index(stage3_io_s2_to_s3_bits_index),
    .io_s2_to_s3_bits_offset(stage3_io_s2_to_s3_bits_offset),
    .io_s2_to_s3_bits_size(stage3_io_s2_to_s3_bits_size),
    .io_s2_to_s3_bits_hit(stage3_io_s2_to_s3_bits_hit),
    .io_s2_to_s3_bits_target_way(stage3_io_s2_to_s3_bits_target_way),
    .io_s2_to_s3_bits_target_line_valid(stage3_io_s2_to_s3_bits_target_line_valid),
    .io_s2_to_s3_bits_target_line_dirty(stage3_io_s2_to_s3_bits_target_line_dirty),
    .io_s2_to_s3_bits_target_line_tag(stage3_io_s2_to_s3_bits_target_line_tag),
    .io_s2_to_s3_bits_target_line_data_0(stage3_io_s2_to_s3_bits_target_line_data_0),
    .io_s2_to_s3_bits_target_line_data_1(stage3_io_s2_to_s3_bits_target_line_data_1),
    .io_s2_to_s3_bits_fencei(stage3_io_s2_to_s3_bits_fencei),
    .io_wt_en(stage3_io_wt_en),
    .io_wt_way(stage3_io_wt_way),
    .io_wt_index(stage3_io_wt_index),
    .io_wt_line_dirty(stage3_io_wt_line_dirty),
    .io_wt_line_tag(stage3_io_wt_line_tag),
    .io_wt_line_data_0(stage3_io_wt_line_data_0),
    .io_wt_line_data_1(stage3_io_wt_line_data_1),
    .io_mem_out_req_ready(stage3_io_mem_out_req_ready),
    .io_mem_out_req_valid(stage3_io_mem_out_req_valid),
    .io_mem_out_req_bits_wr(stage3_io_mem_out_req_bits_wr),
    .io_mem_out_req_bits_addr(stage3_io_mem_out_req_bits_addr),
    .io_mem_out_req_bits_size(stage3_io_mem_out_req_bits_size),
    .io_mem_out_req_bits_wdata(stage3_io_mem_out_req_bits_wdata),
    .io_mem_out_req_bits_wstrb(stage3_io_mem_out_req_bits_wstrb),
    .io_mem_out_req_bits_mthrough(stage3_io_mem_out_req_bits_mthrough),
    .io_mem_out_ret_rdata(stage3_io_mem_out_ret_rdata),
    .io_mem_out_ret_valid(stage3_io_mem_out_ret_valid),
    .io_mem_out_rlast(stage3_io_mem_out_rlast),
    .io_meta_flush(stage3_io_meta_flush),
    .io_rd_en(stage3_io_rd_en),
    .io_rd_index(stage3_io_rd_index),
    .io_rd_lines_0_dirty(stage3_io_rd_lines_0_dirty),
    .io_rd_lines_0_tag(stage3_io_rd_lines_0_tag),
    .io_rd_lines_0_data_0(stage3_io_rd_lines_0_data_0),
    .io_rd_lines_0_data_1(stage3_io_rd_lines_0_data_1),
    .io_rd_lines_1_dirty(stage3_io_rd_lines_1_dirty),
    .io_rd_lines_1_tag(stage3_io_rd_lines_1_tag),
    .io_rd_lines_1_data_0(stage3_io_rd_lines_1_data_0),
    .io_rd_lines_1_data_1(stage3_io_rd_lines_1_data_1),
    .io_rd_lines_2_dirty(stage3_io_rd_lines_2_dirty),
    .io_rd_lines_2_tag(stage3_io_rd_lines_2_tag),
    .io_rd_lines_2_data_0(stage3_io_rd_lines_2_data_0),
    .io_rd_lines_2_data_1(stage3_io_rd_lines_2_data_1),
    .io_rd_lines_3_dirty(stage3_io_rd_lines_3_dirty),
    .io_rd_lines_3_tag(stage3_io_rd_lines_3_tag),
    .io_rd_lines_3_data_0(stage3_io_rd_lines_3_data_0),
    .io_rd_lines_3_data_1(stage3_io_rd_lines_3_data_1)
  );
  ysyx_22051110_CacheMetaRam cache_meta ( // @[CacheTop.scala 84:28]
    .clock(cache_meta_clock),
    .reset(cache_meta_reset),
    .io_flush(cache_meta_io_flush),
    .io_en(cache_meta_io_en),
    .io_wr(cache_meta_io_wr),
    .io_way(cache_meta_io_way),
    .io_index(cache_meta_io_index),
    .io_out_0_valid(cache_meta_io_out_0_valid),
    .io_out_0_dirty(cache_meta_io_out_0_dirty),
    .io_out_0_tag(cache_meta_io_out_0_tag),
    .io_out_1_valid(cache_meta_io_out_1_valid),
    .io_out_1_dirty(cache_meta_io_out_1_dirty),
    .io_out_1_tag(cache_meta_io_out_1_tag),
    .io_out_2_valid(cache_meta_io_out_2_valid),
    .io_out_2_dirty(cache_meta_io_out_2_dirty),
    .io_out_2_tag(cache_meta_io_out_2_tag),
    .io_out_3_valid(cache_meta_io_out_3_valid),
    .io_out_3_dirty(cache_meta_io_out_3_dirty),
    .io_out_3_tag(cache_meta_io_out_3_tag),
    .io_in_dirty(cache_meta_io_in_dirty),
    .io_in_tag(cache_meta_io_in_tag)
  );
  assign io_in_req_ready = stage1_io_cpu_ready; // @[CacheTop.scala 126:19]
  assign io_in_ret_rdata = stage3_io_cpu_rdata; // @[CacheTop.scala 127:19]
  assign io_in_ret_valid = stage3_io_cpu_valid; // @[CacheTop.scala 127:19]
  assign io_out_req_valid = stage3_io_mem_out_req_valid; // @[CacheTop.scala 129:12]
  assign io_out_req_bits_wr = stage3_io_mem_out_req_bits_wr; // @[CacheTop.scala 129:12]
  assign io_out_req_bits_addr = stage3_io_mem_out_req_bits_addr; // @[CacheTop.scala 129:12]
  assign io_out_req_bits_size = stage3_io_mem_out_req_bits_size; // @[CacheTop.scala 129:12]
  assign io_out_req_bits_wdata = stage3_io_mem_out_req_bits_wdata; // @[CacheTop.scala 129:12]
  assign io_out_req_bits_wstrb = stage3_io_mem_out_req_bits_wstrb; // @[CacheTop.scala 129:12]
  assign io_out_req_bits_mthrough = stage3_io_mem_out_req_bits_mthrough; // @[CacheTop.scala 129:12]
  assign io_flush = stage3_io_meta_flush; // @[CacheTop.scala 86:28]
  assign io_cache_data_0_addr = stage3_io_rd_en ? {{1'd0}, stage3_io_rd_index} : _cache_addr_T; // @[CacheTop.scala 82:28]
  assign io_cache_data_0_cen = ~(stage1_io_rd_en | stage3_io_rd_en | stage3_io_wt_en); // @[CacheTop.scala 100:35]
  assign io_cache_data_0_wen = ~(stage3_io_wt_en & stage3_io_wt_way == 2'h0); // @[CacheTop.scala 101:35]
  assign io_cache_data_0_wdata = {stage3_io_wt_line_data_1,stage3_io_wt_line_data_0}; // @[Cat.scala 33:92]
  assign io_cache_data_1_addr = stage3_io_rd_en ? {{1'd0}, stage3_io_rd_index} : _cache_addr_T; // @[CacheTop.scala 82:28]
  assign io_cache_data_1_cen = ~(stage1_io_rd_en | stage3_io_rd_en | stage3_io_wt_en); // @[CacheTop.scala 100:35]
  assign io_cache_data_1_wen = ~(stage3_io_wt_en & stage3_io_wt_way == 2'h1); // @[CacheTop.scala 101:35]
  assign io_cache_data_1_wdata = {stage3_io_wt_line_data_1,stage3_io_wt_line_data_0}; // @[Cat.scala 33:92]
  assign io_cache_data_2_addr = stage3_io_rd_en ? {{1'd0}, stage3_io_rd_index} : _cache_addr_T; // @[CacheTop.scala 82:28]
  assign io_cache_data_2_cen = ~(stage1_io_rd_en | stage3_io_rd_en | stage3_io_wt_en); // @[CacheTop.scala 100:35]
  assign io_cache_data_2_wen = ~(stage3_io_wt_en & stage3_io_wt_way == 2'h2); // @[CacheTop.scala 101:35]
  assign io_cache_data_2_wdata = {stage3_io_wt_line_data_1,stage3_io_wt_line_data_0}; // @[Cat.scala 33:92]
  assign io_cache_data_3_addr = stage3_io_rd_en ? {{1'd0}, stage3_io_rd_index} : _cache_addr_T; // @[CacheTop.scala 82:28]
  assign io_cache_data_3_cen = ~(stage1_io_rd_en | stage3_io_rd_en | stage3_io_wt_en); // @[CacheTop.scala 100:35]
  assign io_cache_data_3_wen = ~(stage3_io_wt_en & stage3_io_wt_way == 2'h3); // @[CacheTop.scala 101:35]
  assign io_cache_data_3_wdata = {stage3_io_wt_line_data_1,stage3_io_wt_line_data_0}; // @[Cat.scala 33:92]
  assign stage1_io_cpu_valid = io_in_req_valid; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_wr = io_in_req_bits_wr; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_addr = io_in_req_bits_addr; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_size = io_in_req_bits_size; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_wdata = io_in_req_bits_wdata; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_wstrb = io_in_req_bits_wstrb; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_mthrough = io_in_req_bits_mthrough; // @[CacheTop.scala 126:19]
  assign stage1_io_cpu_bits_fencei = io_in_req_bits_fencei; // @[CacheTop.scala 126:19]
  assign stage1_io_s1_to_s2_ready = stage2_io_s1_to_s2_ready; // @[CacheTop.scala 123:24]
  assign stage2_clock = clock;
  assign stage2_reset = reset;
  assign stage2_io_s1_to_s2_valid = stage1_io_s1_to_s2_valid; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_wr = stage1_io_s1_to_s2_bits_wr; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_wdata = stage1_io_s1_to_s2_bits_wdata; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_wstrb = stage1_io_s1_to_s2_bits_wstrb; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_mthrough = stage1_io_s1_to_s2_bits_mthrough; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_tag = stage1_io_s1_to_s2_bits_tag; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_index = stage1_io_s1_to_s2_bits_index; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_offset = stage1_io_s1_to_s2_bits_offset; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_size = stage1_io_s1_to_s2_bits_size; // @[CacheTop.scala 123:24]
  assign stage2_io_s1_to_s2_bits_fencei = stage1_io_s1_to_s2_bits_fencei; // @[CacheTop.scala 123:24]
  assign stage2_io_rd_lines_0_valid = cache_meta_io_out_0_valid; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_0_dirty = cache_meta_io_out_0_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_0_tag = cache_meta_io_out_0_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_0_data_0 = io_cache_data_0_rdata[63:0]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_0_data_1 = io_cache_data_0_rdata[127:64]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_1_valid = cache_meta_io_out_1_valid; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_1_dirty = cache_meta_io_out_1_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_1_tag = cache_meta_io_out_1_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_1_data_0 = io_cache_data_1_rdata[63:0]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_1_data_1 = io_cache_data_1_rdata[127:64]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_2_valid = cache_meta_io_out_2_valid; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_2_dirty = cache_meta_io_out_2_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_2_tag = cache_meta_io_out_2_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_2_data_0 = io_cache_data_2_rdata[63:0]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_2_data_1 = io_cache_data_2_rdata[127:64]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_3_valid = cache_meta_io_out_3_valid; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_3_dirty = cache_meta_io_out_3_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_3_tag = cache_meta_io_out_3_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage2_io_rd_lines_3_data_0 = io_cache_data_3_rdata[63:0]; // @[CacheTop.scala 116:61]
  assign stage2_io_rd_lines_3_data_1 = io_cache_data_3_rdata[127:64]; // @[CacheTop.scala 116:61]
  assign stage2_io_s2_to_s3_ready = stage3_io_s2_to_s3_ready; // @[CacheTop.scala 124:24]
  assign stage3_clock = clock;
  assign stage3_reset = reset;
  assign stage3_io_s2_to_s3_valid = stage2_io_s2_to_s3_valid; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_wr = stage2_io_s2_to_s3_bits_wr; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_wdata = stage2_io_s2_to_s3_bits_wdata; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_wstrb = stage2_io_s2_to_s3_bits_wstrb; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_mthrough = stage2_io_s2_to_s3_bits_mthrough; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_tag = stage2_io_s2_to_s3_bits_tag; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_index = stage2_io_s2_to_s3_bits_index; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_offset = stage2_io_s2_to_s3_bits_offset; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_size = stage2_io_s2_to_s3_bits_size; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_hit = stage2_io_s2_to_s3_bits_hit; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_target_way = stage2_io_s2_to_s3_bits_target_way; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_target_line_valid = stage2_io_s2_to_s3_bits_target_line_valid; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_target_line_dirty = stage2_io_s2_to_s3_bits_target_line_dirty; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_target_line_tag = stage2_io_s2_to_s3_bits_target_line_tag; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_target_line_data_0 = stage2_io_s2_to_s3_bits_target_line_data_0; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_target_line_data_1 = stage2_io_s2_to_s3_bits_target_line_data_1; // @[CacheTop.scala 124:24]
  assign stage3_io_s2_to_s3_bits_fencei = stage2_io_s2_to_s3_bits_fencei; // @[CacheTop.scala 124:24]
  assign stage3_io_mem_out_req_ready = io_out_req_ready; // @[CacheTop.scala 129:12]
  assign stage3_io_mem_out_ret_rdata = io_out_ret_rdata; // @[CacheTop.scala 129:12]
  assign stage3_io_mem_out_ret_valid = io_out_ret_valid; // @[CacheTop.scala 129:12]
  assign stage3_io_mem_out_rlast = io_out_rlast; // @[CacheTop.scala 129:12]
  assign stage3_io_rd_lines_0_dirty = cache_meta_io_out_0_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_0_tag = cache_meta_io_out_0_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_0_data_0 = io_cache_data_0_rdata[63:0]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_0_data_1 = io_cache_data_0_rdata[127:64]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_1_dirty = cache_meta_io_out_1_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_1_tag = cache_meta_io_out_1_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_1_data_0 = io_cache_data_1_rdata[63:0]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_1_data_1 = io_cache_data_1_rdata[127:64]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_2_dirty = cache_meta_io_out_2_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_2_tag = cache_meta_io_out_2_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_2_data_0 = io_cache_data_2_rdata[63:0]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_2_data_1 = io_cache_data_2_rdata[127:64]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_3_dirty = cache_meta_io_out_3_dirty; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_3_tag = cache_meta_io_out_3_tag; // @[CacheTop.scala 64:26 92:45]
  assign stage3_io_rd_lines_3_data_0 = io_cache_data_3_rdata[63:0]; // @[CacheTop.scala 117:61]
  assign stage3_io_rd_lines_3_data_1 = io_cache_data_3_rdata[127:64]; // @[CacheTop.scala 117:61]
  assign cache_meta_clock = clock;
  assign cache_meta_reset = reset;
  assign cache_meta_io_flush = stage3_io_meta_flush; // @[CacheTop.scala 87:25]
  assign cache_meta_io_en = stage1_io_rd_en | stage3_io_wt_en | stage3_io_rd_en; // @[CacheTop.scala 88:63]
  assign cache_meta_io_wr = stage3_io_wt_en; // @[CacheTop.scala 89:25]
  assign cache_meta_io_way = stage3_io_wt_way; // @[CacheTop.scala 90:25]
  assign cache_meta_io_index = cache_addr[4:0]; // @[CacheTop.scala 91:25]
  assign cache_meta_io_in_dirty = stage3_io_wt_line_dirty; // @[CacheTop.scala 94:28]
  assign cache_meta_io_in_tag = stage3_io_wt_line_tag; // @[CacheTop.scala 95:28]
endmodule
module ysyx_22051110_Clint(
  input         clock,
  input         reset,
  input         io_in_en,
  input         io_in_wr,
  input  [31:0] io_in_addr,
  input  [63:0] io_in_wdata,
  output        io_in_clint_hit,
  output        io_in_ret_valid,
  output [63:0] io_in_rdata,
  output        io_has_intr_t,
  output        io_clr_intr_t
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
  reg [63:0] _RAND_1;
  reg [63:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] mtime; // @[Clint.scala 21:32]
  reg [63:0] mtimecmp; // @[Clint.scala 22:32]
  wire [63:0] _GEN_6 = {{32'd0}, io_in_addr}; // @[Clint.scala 23:36]
  wire  hit_mtime = _GEN_6 == 64'h200bff8; // @[Clint.scala 23:36]
  wire  hit_mtimecmp = _GEN_6 == 64'h2004000; // @[Clint.scala 24:36]
  wire  wen = io_in_en & io_in_wr; // @[Clint.scala 25:34]
  wire  ren = io_in_en & ~io_in_wr; // @[Clint.scala 26:34]
  reg [63:0] rdata; // @[Clint.scala 27:32]
  wire [63:0] _mtime_T_1 = mtime + 64'h1; // @[Clint.scala 34:27]
  wire  _T_2 = ren & hit_mtimecmp; // @[Clint.scala 36:14]
  wire  _T_3 = ren & hit_mtime; // @[Clint.scala 39:21]
  reg  ret_valid; // @[Clint.scala 46:36]
  wire  _GEN_4 = ret_valid ? 1'h0 : ret_valid; // @[Clint.scala 49:35 50:19 46:36]
  wire  _GEN_5 = io_in_en & io_in_clint_hit | _GEN_4; // @[Clint.scala 47:38 48:19]
  assign io_in_clint_hit = hit_mtime | hit_mtimecmp; // @[Clint.scala 45:39]
  assign io_in_ret_valid = ret_valid; // @[Clint.scala 52:21]
  assign io_in_rdata = rdata; // @[Clint.scala 43:17]
  assign io_has_intr_t = mtime >= mtimecmp; // @[Clint.scala 54:29]
  assign io_clr_intr_t = wen & hit_mtimecmp; // @[Clint.scala 55:26]
  always @(posedge clock) begin
    if (reset) begin // @[Clint.scala 21:32]
      mtime <= 64'h0; // @[Clint.scala 21:32]
    end else if (wen & hit_mtime) begin // @[Clint.scala 31:27]
      mtime <= io_in_wdata; // @[Clint.scala 32:18]
    end else begin
      mtime <= _mtime_T_1; // @[Clint.scala 34:18]
    end
    if (reset) begin // @[Clint.scala 22:32]
      mtimecmp <= 64'h0; // @[Clint.scala 22:32]
    end else if (wen & hit_mtimecmp) begin // @[Clint.scala 28:30]
      mtimecmp <= io_in_wdata; // @[Clint.scala 29:18]
    end
    if (reset) begin // @[Clint.scala 27:32]
      rdata <= 64'h0; // @[Clint.scala 27:32]
    end else if (_T_2) begin // @[Clint.scala 37:5]
      rdata <= mtimecmp; // @[Clint.scala 38:15]
    end else if (_T_3) begin // @[Clint.scala 40:5]
      rdata <= mtime; // @[Clint.scala 41:15]
    end
    if (reset) begin // @[Clint.scala 46:36]
      ret_valid <= 1'h0; // @[Clint.scala 46:36]
    end else begin
      ret_valid <= _GEN_5;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  mtime = _RAND_0[63:0];
  _RAND_1 = {2{`RANDOM}};
  mtimecmp = _RAND_1[63:0];
  _RAND_2 = {2{`RANDOM}};
  rdata = _RAND_2[63:0];
  _RAND_3 = {1{`RANDOM}};
  ret_valid = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110_Arbiter(
  output        io_in_0_ready,
  input         io_in_0_valid,
  input  [31:0] io_in_0_bits_araddr,
  input  [7:0]  io_in_0_bits_arlen,
  input  [2:0]  io_in_0_bits_arsize,
  output        io_in_1_ready,
  input         io_in_1_valid,
  input  [31:0] io_in_1_bits_araddr,
  input  [7:0]  io_in_1_bits_arlen,
  input  [2:0]  io_in_1_bits_arsize,
  input         io_out_ready,
  output        io_out_valid,
  output [31:0] io_out_bits_araddr,
  output [7:0]  io_out_bits_arlen,
  output [2:0]  io_out_bits_arsize,
  output        io_chosen
);
  wire  grant_1 = ~io_in_0_valid; // @[Arbiter.scala 45:78]
  assign io_in_0_ready = io_out_ready; // @[Arbiter.scala 146:19]
  assign io_in_1_ready = grant_1 & io_out_ready; // @[Arbiter.scala 146:19]
  assign io_out_valid = ~grant_1 | io_in_1_valid; // @[Arbiter.scala 147:31]
  assign io_out_bits_araddr = io_in_0_valid ? io_in_0_bits_araddr : io_in_1_bits_araddr; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_arlen = io_in_0_valid ? io_in_0_bits_arlen : io_in_1_bits_arlen; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_arsize = io_in_0_valid ? io_in_0_bits_arsize : io_in_1_bits_arsize; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_chosen = io_in_0_valid ? 1'h0 : 1'h1; // @[Arbiter.scala 135:13 138:26 139:17]
endmodule
module ysyx_22051110_Arbiter_1(
  output        io_in_0_ready,
  input         io_in_0_valid,
  input  [31:0] io_in_0_bits_awaddr,
  input  [7:0]  io_in_0_bits_awlen,
  input  [2:0]  io_in_0_bits_awsize,
  output        io_in_1_ready,
  input         io_in_1_valid,
  input  [31:0] io_in_1_bits_awaddr,
  input  [7:0]  io_in_1_bits_awlen,
  input  [2:0]  io_in_1_bits_awsize,
  input         io_out_ready,
  output        io_out_valid,
  output [31:0] io_out_bits_awaddr,
  output [7:0]  io_out_bits_awlen,
  output [2:0]  io_out_bits_awsize,
  output        io_chosen
);
  wire  grant_1 = ~io_in_0_valid; // @[Arbiter.scala 45:78]
  assign io_in_0_ready = io_out_ready; // @[Arbiter.scala 146:19]
  assign io_in_1_ready = grant_1 & io_out_ready; // @[Arbiter.scala 146:19]
  assign io_out_valid = ~grant_1 | io_in_1_valid; // @[Arbiter.scala 147:31]
  assign io_out_bits_awaddr = io_in_0_valid ? io_in_0_bits_awaddr : io_in_1_bits_awaddr; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_awlen = io_in_0_valid ? io_in_0_bits_awlen : io_in_1_bits_awlen; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_out_bits_awsize = io_in_0_valid ? io_in_0_bits_awsize : io_in_1_bits_awsize; // @[Arbiter.scala 136:15 138:26 140:19]
  assign io_chosen = io_in_0_valid ? 1'h0 : 1'h1; // @[Arbiter.scala 135:13 138:26 139:17]
endmodule
module ysyx_22051110_AXIArbiter(
  input         clock,
  input         reset,
  output        io_in_0_ar_ready,
  input         io_in_0_ar_valid,
  input  [31:0] io_in_0_ar_bits_araddr,
  input  [7:0]  io_in_0_ar_bits_arlen,
  input  [2:0]  io_in_0_ar_bits_arsize,
  input         io_in_0_rd_ready,
  output        io_in_0_rd_valid,
  output [63:0] io_in_0_rd_bits_rdata,
  output        io_in_0_rd_bits_rlast,
  output        io_in_0_aw_ready,
  input         io_in_0_aw_valid,
  input  [31:0] io_in_0_aw_bits_awaddr,
  input  [7:0]  io_in_0_aw_bits_awlen,
  input  [2:0]  io_in_0_aw_bits_awsize,
  output        io_in_0_wt_ready,
  input         io_in_0_wt_valid,
  input  [63:0] io_in_0_wt_bits_wdata,
  input  [7:0]  io_in_0_wt_bits_wstrb,
  input         io_in_0_wt_bits_wlast,
  input         io_in_0_b_ready,
  output        io_in_0_b_valid,
  output        io_in_1_ar_ready,
  input         io_in_1_ar_valid,
  input  [31:0] io_in_1_ar_bits_araddr,
  input  [7:0]  io_in_1_ar_bits_arlen,
  input  [2:0]  io_in_1_ar_bits_arsize,
  input         io_in_1_rd_ready,
  output        io_in_1_rd_valid,
  output [63:0] io_in_1_rd_bits_rdata,
  output        io_in_1_rd_bits_rlast,
  output        io_in_1_aw_ready,
  input         io_in_1_aw_valid,
  input  [31:0] io_in_1_aw_bits_awaddr,
  input  [7:0]  io_in_1_aw_bits_awlen,
  input  [2:0]  io_in_1_aw_bits_awsize,
  output        io_in_1_wt_ready,
  input         io_in_1_wt_valid,
  input  [63:0] io_in_1_wt_bits_wdata,
  input  [7:0]  io_in_1_wt_bits_wstrb,
  input         io_in_1_wt_bits_wlast,
  input         io_in_1_b_ready,
  output        io_in_1_b_valid,
  input         io_out_ar_ready,
  output        io_out_ar_valid,
  output [31:0] io_out_ar_bits_araddr,
  output [7:0]  io_out_ar_bits_arlen,
  output [2:0]  io_out_ar_bits_arsize,
  output        io_out_rd_ready,
  input         io_out_rd_valid,
  input  [63:0] io_out_rd_bits_rdata,
  input         io_out_rd_bits_rlast,
  input         io_out_aw_ready,
  output        io_out_aw_valid,
  output [31:0] io_out_aw_bits_awaddr,
  output [7:0]  io_out_aw_bits_awlen,
  output [2:0]  io_out_aw_bits_awsize,
  input         io_out_wt_ready,
  output        io_out_wt_valid,
  output [63:0] io_out_wt_bits_wdata,
  output [7:0]  io_out_wt_bits_wstrb,
  output        io_out_wt_bits_wlast,
  output        io_out_b_ready,
  input         io_out_b_valid
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  arbiter_rd_io_in_0_ready; // @[AXIArbiter.scala 13:28]
  wire  arbiter_rd_io_in_0_valid; // @[AXIArbiter.scala 13:28]
  wire [31:0] arbiter_rd_io_in_0_bits_araddr; // @[AXIArbiter.scala 13:28]
  wire [7:0] arbiter_rd_io_in_0_bits_arlen; // @[AXIArbiter.scala 13:28]
  wire [2:0] arbiter_rd_io_in_0_bits_arsize; // @[AXIArbiter.scala 13:28]
  wire  arbiter_rd_io_in_1_ready; // @[AXIArbiter.scala 13:28]
  wire  arbiter_rd_io_in_1_valid; // @[AXIArbiter.scala 13:28]
  wire [31:0] arbiter_rd_io_in_1_bits_araddr; // @[AXIArbiter.scala 13:28]
  wire [7:0] arbiter_rd_io_in_1_bits_arlen; // @[AXIArbiter.scala 13:28]
  wire [2:0] arbiter_rd_io_in_1_bits_arsize; // @[AXIArbiter.scala 13:28]
  wire  arbiter_rd_io_out_ready; // @[AXIArbiter.scala 13:28]
  wire  arbiter_rd_io_out_valid; // @[AXIArbiter.scala 13:28]
  wire [31:0] arbiter_rd_io_out_bits_araddr; // @[AXIArbiter.scala 13:28]
  wire [7:0] arbiter_rd_io_out_bits_arlen; // @[AXIArbiter.scala 13:28]
  wire [2:0] arbiter_rd_io_out_bits_arsize; // @[AXIArbiter.scala 13:28]
  wire  arbiter_rd_io_chosen; // @[AXIArbiter.scala 13:28]
  wire  arbiter_wt_io_in_0_ready; // @[AXIArbiter.scala 45:28]
  wire  arbiter_wt_io_in_0_valid; // @[AXIArbiter.scala 45:28]
  wire [31:0] arbiter_wt_io_in_0_bits_awaddr; // @[AXIArbiter.scala 45:28]
  wire [7:0] arbiter_wt_io_in_0_bits_awlen; // @[AXIArbiter.scala 45:28]
  wire [2:0] arbiter_wt_io_in_0_bits_awsize; // @[AXIArbiter.scala 45:28]
  wire  arbiter_wt_io_in_1_ready; // @[AXIArbiter.scala 45:28]
  wire  arbiter_wt_io_in_1_valid; // @[AXIArbiter.scala 45:28]
  wire [31:0] arbiter_wt_io_in_1_bits_awaddr; // @[AXIArbiter.scala 45:28]
  wire [7:0] arbiter_wt_io_in_1_bits_awlen; // @[AXIArbiter.scala 45:28]
  wire [2:0] arbiter_wt_io_in_1_bits_awsize; // @[AXIArbiter.scala 45:28]
  wire  arbiter_wt_io_out_ready; // @[AXIArbiter.scala 45:28]
  wire  arbiter_wt_io_out_valid; // @[AXIArbiter.scala 45:28]
  wire [31:0] arbiter_wt_io_out_bits_awaddr; // @[AXIArbiter.scala 45:28]
  wire [7:0] arbiter_wt_io_out_bits_awlen; // @[AXIArbiter.scala 45:28]
  wire [2:0] arbiter_wt_io_out_bits_awsize; // @[AXIArbiter.scala 45:28]
  wire  arbiter_wt_io_chosen; // @[AXIArbiter.scala 45:28]
  reg  rd_chosen; // @[AXIArbiter.scala 14:29]
  reg  occupied; // @[AXIArbiter.scala 15:29]
  wire  _T = ~occupied; // @[AXIArbiter.scala 16:29]
  wire  _T_2 = io_out_rd_ready & io_out_rd_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_1 = _T_2 & io_out_rd_bits_rlast ? 1'h0 : occupied; // @[AXIArbiter.scala 21:66 22:18 15:29]
  wire  _GEN_2 = io_out_ar_valid | _GEN_1; // @[AXIArbiter.scala 19:26 20:18]
  wire  _arbiter_rd_io_in_0_valid_T_1 = ~rd_chosen; // @[AXIArbiter.scala 27:97]
  wire  _arbiter_rd_io_in_0_valid_T_3 = _T | occupied & ~rd_chosen; // @[AXIArbiter.scala 27:70]
  wire  _arbiter_rd_io_in_1_valid_T_3 = _T | occupied & rd_chosen; // @[AXIArbiter.scala 27:70]
  reg  wt_chosen; // @[AXIArbiter.scala 46:29]
  wire  _T_5 = io_out_aw_ready & io_out_aw_valid; // @[Decoupled.scala 52:35]
  wire  _io_in_0_wt_ready_T = ~wt_chosen; // @[AXIArbiter.scala 63:60]
  ysyx_22051110_Arbiter arbiter_rd ( // @[AXIArbiter.scala 13:28]
    .io_in_0_ready(arbiter_rd_io_in_0_ready),
    .io_in_0_valid(arbiter_rd_io_in_0_valid),
    .io_in_0_bits_araddr(arbiter_rd_io_in_0_bits_araddr),
    .io_in_0_bits_arlen(arbiter_rd_io_in_0_bits_arlen),
    .io_in_0_bits_arsize(arbiter_rd_io_in_0_bits_arsize),
    .io_in_1_ready(arbiter_rd_io_in_1_ready),
    .io_in_1_valid(arbiter_rd_io_in_1_valid),
    .io_in_1_bits_araddr(arbiter_rd_io_in_1_bits_araddr),
    .io_in_1_bits_arlen(arbiter_rd_io_in_1_bits_arlen),
    .io_in_1_bits_arsize(arbiter_rd_io_in_1_bits_arsize),
    .io_out_ready(arbiter_rd_io_out_ready),
    .io_out_valid(arbiter_rd_io_out_valid),
    .io_out_bits_araddr(arbiter_rd_io_out_bits_araddr),
    .io_out_bits_arlen(arbiter_rd_io_out_bits_arlen),
    .io_out_bits_arsize(arbiter_rd_io_out_bits_arsize),
    .io_chosen(arbiter_rd_io_chosen)
  );
  ysyx_22051110_Arbiter_1 arbiter_wt ( // @[AXIArbiter.scala 45:28]
    .io_in_0_ready(arbiter_wt_io_in_0_ready),
    .io_in_0_valid(arbiter_wt_io_in_0_valid),
    .io_in_0_bits_awaddr(arbiter_wt_io_in_0_bits_awaddr),
    .io_in_0_bits_awlen(arbiter_wt_io_in_0_bits_awlen),
    .io_in_0_bits_awsize(arbiter_wt_io_in_0_bits_awsize),
    .io_in_1_ready(arbiter_wt_io_in_1_ready),
    .io_in_1_valid(arbiter_wt_io_in_1_valid),
    .io_in_1_bits_awaddr(arbiter_wt_io_in_1_bits_awaddr),
    .io_in_1_bits_awlen(arbiter_wt_io_in_1_bits_awlen),
    .io_in_1_bits_awsize(arbiter_wt_io_in_1_bits_awsize),
    .io_out_ready(arbiter_wt_io_out_ready),
    .io_out_valid(arbiter_wt_io_out_valid),
    .io_out_bits_awaddr(arbiter_wt_io_out_bits_awaddr),
    .io_out_bits_awlen(arbiter_wt_io_out_bits_awlen),
    .io_out_bits_awsize(arbiter_wt_io_out_bits_awsize),
    .io_chosen(arbiter_wt_io_chosen)
  );
  assign io_in_0_ar_ready = arbiter_rd_io_in_0_ready & _arbiter_rd_io_in_0_valid_T_3; // @[AXIArbiter.scala 29:64]
  assign io_in_0_rd_valid = io_out_rd_valid & _arbiter_rd_io_in_0_valid_T_1; // @[AXIArbiter.scala 37:46]
  assign io_in_0_rd_bits_rdata = io_out_rd_bits_rdata; // @[AXIArbiter.scala 38:27]
  assign io_in_0_rd_bits_rlast = io_out_rd_bits_rlast; // @[AXIArbiter.scala 38:27]
  assign io_in_0_aw_ready = arbiter_wt_io_in_0_ready; // @[AXIArbiter.scala 55:35]
  assign io_in_0_wt_ready = io_out_wt_ready & ~wt_chosen; // @[AXIArbiter.scala 63:46]
  assign io_in_0_b_valid = io_out_b_valid & _io_in_0_wt_ready_T; // @[AXIArbiter.scala 64:45]
  assign io_in_1_ar_ready = arbiter_rd_io_in_1_ready & _arbiter_rd_io_in_1_valid_T_3; // @[AXIArbiter.scala 29:64]
  assign io_in_1_rd_valid = io_out_rd_valid & rd_chosen; // @[AXIArbiter.scala 37:46]
  assign io_in_1_rd_bits_rdata = io_out_rd_bits_rdata; // @[AXIArbiter.scala 38:27]
  assign io_in_1_rd_bits_rlast = io_out_rd_bits_rlast; // @[AXIArbiter.scala 38:27]
  assign io_in_1_aw_ready = arbiter_wt_io_in_1_ready; // @[AXIArbiter.scala 55:35]
  assign io_in_1_wt_ready = io_out_wt_ready & wt_chosen; // @[AXIArbiter.scala 63:46]
  assign io_in_1_b_valid = io_out_b_valid & wt_chosen; // @[AXIArbiter.scala 64:45]
  assign io_out_ar_valid = arbiter_rd_io_out_valid; // @[AXIArbiter.scala 33:31]
  assign io_out_ar_bits_araddr = arbiter_rd_io_out_bits_araddr; // @[AXIArbiter.scala 34:31]
  assign io_out_ar_bits_arlen = arbiter_rd_io_out_bits_arlen; // @[AXIArbiter.scala 34:31]
  assign io_out_ar_bits_arsize = arbiter_rd_io_out_bits_arsize; // @[AXIArbiter.scala 34:31]
  assign io_out_rd_ready = rd_chosen ? io_in_1_rd_ready : io_in_0_rd_ready; // @[AXIArbiter.scala 40:{23,23}]
  assign io_out_aw_valid = arbiter_wt_io_out_valid; // @[AXIArbiter.scala 59:31]
  assign io_out_aw_bits_awaddr = arbiter_wt_io_out_bits_awaddr; // @[AXIArbiter.scala 60:31]
  assign io_out_aw_bits_awlen = arbiter_wt_io_out_bits_awlen; // @[AXIArbiter.scala 60:31]
  assign io_out_aw_bits_awsize = arbiter_wt_io_out_bits_awsize; // @[AXIArbiter.scala 60:31]
  assign io_out_wt_valid = wt_chosen ? io_in_1_wt_valid : io_in_0_wt_valid; // @[AXIArbiter.scala 68:{29,29}]
  assign io_out_wt_bits_wdata = wt_chosen ? io_in_1_wt_bits_wdata : io_in_0_wt_bits_wdata; // @[AXIArbiter.scala 67:{29,29}]
  assign io_out_wt_bits_wstrb = wt_chosen ? io_in_1_wt_bits_wstrb : io_in_0_wt_bits_wstrb; // @[AXIArbiter.scala 67:{29,29}]
  assign io_out_wt_bits_wlast = wt_chosen ? io_in_1_wt_bits_wlast : io_in_0_wt_bits_wlast; // @[AXIArbiter.scala 67:{29,29}]
  assign io_out_b_ready = wt_chosen ? io_in_1_b_ready : io_in_0_b_ready; // @[AXIArbiter.scala 69:{29,29}]
  assign arbiter_rd_io_in_0_valid = io_in_0_ar_valid & (_T | occupied & ~rd_chosen); // @[AXIArbiter.scala 27:56]
  assign arbiter_rd_io_in_0_bits_araddr = io_in_0_ar_bits_araddr; // @[AXIArbiter.scala 28:35]
  assign arbiter_rd_io_in_0_bits_arlen = io_in_0_ar_bits_arlen; // @[AXIArbiter.scala 28:35]
  assign arbiter_rd_io_in_0_bits_arsize = io_in_0_ar_bits_arsize; // @[AXIArbiter.scala 28:35]
  assign arbiter_rd_io_in_1_valid = io_in_1_ar_valid & (_T | occupied & rd_chosen); // @[AXIArbiter.scala 27:56]
  assign arbiter_rd_io_in_1_bits_araddr = io_in_1_ar_bits_araddr; // @[AXIArbiter.scala 28:35]
  assign arbiter_rd_io_in_1_bits_arlen = io_in_1_ar_bits_arlen; // @[AXIArbiter.scala 28:35]
  assign arbiter_rd_io_in_1_bits_arsize = io_in_1_ar_bits_arsize; // @[AXIArbiter.scala 28:35]
  assign arbiter_rd_io_out_ready = io_out_ar_ready; // @[AXIArbiter.scala 32:31]
  assign arbiter_wt_io_in_0_valid = io_in_0_aw_valid; // @[AXIArbiter.scala 53:35]
  assign arbiter_wt_io_in_0_bits_awaddr = io_in_0_aw_bits_awaddr; // @[AXIArbiter.scala 54:35]
  assign arbiter_wt_io_in_0_bits_awlen = io_in_0_aw_bits_awlen; // @[AXIArbiter.scala 54:35]
  assign arbiter_wt_io_in_0_bits_awsize = io_in_0_aw_bits_awsize; // @[AXIArbiter.scala 54:35]
  assign arbiter_wt_io_in_1_valid = io_in_1_aw_valid; // @[AXIArbiter.scala 53:35]
  assign arbiter_wt_io_in_1_bits_awaddr = io_in_1_aw_bits_awaddr; // @[AXIArbiter.scala 54:35]
  assign arbiter_wt_io_in_1_bits_awlen = io_in_1_aw_bits_awlen; // @[AXIArbiter.scala 54:35]
  assign arbiter_wt_io_in_1_bits_awsize = io_in_1_aw_bits_awsize; // @[AXIArbiter.scala 54:35]
  assign arbiter_wt_io_out_ready = io_out_aw_ready; // @[AXIArbiter.scala 58:31]
  always @(posedge clock) begin
    if (reset) begin // @[AXIArbiter.scala 14:29]
      rd_chosen <= 1'h0; // @[AXIArbiter.scala 14:29]
    end else if (io_out_ar_valid & ~occupied) begin // @[AXIArbiter.scala 16:39]
      rd_chosen <= arbiter_rd_io_chosen; // @[AXIArbiter.scala 17:19]
    end
    if (reset) begin // @[AXIArbiter.scala 15:29]
      occupied <= 1'h0; // @[AXIArbiter.scala 15:29]
    end else begin
      occupied <= _GEN_2;
    end
    if (reset) begin // @[AXIArbiter.scala 46:29]
      wt_chosen <= 1'h0; // @[AXIArbiter.scala 46:29]
    end else if (_T_5) begin // @[AXIArbiter.scala 47:25]
      wt_chosen <= arbiter_wt_io_chosen; // @[AXIArbiter.scala 48:19]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  rd_chosen = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  occupied = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  wt_chosen = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ysyx_22051110(
  input          clock,
  input          reset,
  input          io_interrupt,
  input          io_master_awready,
  output         io_master_awvalid,
  output [3:0]   io_master_awid,
  output [31:0]  io_master_awaddr,
  output [7:0]   io_master_awlen,
  output [2:0]   io_master_awsize,
  output [1:0]   io_master_awburst,
  input          io_master_wready,
  output         io_master_wvalid,
  output [63:0]  io_master_wdata,
  output [7:0]   io_master_wstrb,
  output         io_master_wlast,
  output         io_master_bready,
  input          io_master_bvalid,
  input  [3:0]   io_master_bid,
  input  [1:0]   io_master_bresp,
  input          io_master_arready,
  output         io_master_arvalid,
  output [3:0]   io_master_arid,
  output [31:0]  io_master_araddr,
  output [7:0]   io_master_arlen,
  output [2:0]   io_master_arsize,
  output [1:0]   io_master_arburst,
  output         io_master_rready,
  input          io_master_rvalid,
  input  [3:0]   io_master_rid,
  input  [1:0]   io_master_rresp,
  input  [63:0]  io_master_rdata,
  input          io_master_rlast,
  output         io_slave_awready,
  input          io_slave_awvalid,
  input  [3:0]   io_slave_awid,
  input  [31:0]  io_slave_awaddr,
  input  [7:0]   io_slave_awlen,
  input  [2:0]   io_slave_awsize,
  input  [1:0]   io_slave_awburst,
  output         io_slave_wready,
  input          io_slave_wvalid,
  input  [63:0]  io_slave_wdata,
  input  [7:0]   io_slave_wstrb,
  input          io_slave_wlast,
  input          io_slave_bready,
  output         io_slave_bvalid,
  output [3:0]   io_slave_bid,
  output [1:0]   io_slave_bresp,
  output         io_slave_arready,
  input          io_slave_arvalid,
  input  [3:0]   io_slave_arid,
  input  [31:0]  io_slave_araddr,
  input  [7:0]   io_slave_arlen,
  input  [2:0]   io_slave_arsize,
  input  [1:0]   io_slave_arburst,
  input          io_slave_rready,
  output         io_slave_rvalid,
  output [3:0]   io_slave_rid,
  output [1:0]   io_slave_rresp,
  output [63:0]  io_slave_rdata,
  output         io_slave_rlast,
  output [5:0]   io_sram0_addr,
  output         io_sram0_cen,
  output         io_sram0_wen,
  output [127:0] io_sram0_wmask,
  output [127:0] io_sram0_wdata,
  input  [127:0] io_sram0_rdata,
  output [5:0]   io_sram1_addr,
  output         io_sram1_cen,
  output         io_sram1_wen,
  output [127:0] io_sram1_wmask,
  output [127:0] io_sram1_wdata,
  input  [127:0] io_sram1_rdata,
  output [5:0]   io_sram2_addr,
  output         io_sram2_cen,
  output         io_sram2_wen,
  output [127:0] io_sram2_wmask,
  output [127:0] io_sram2_wdata,
  input  [127:0] io_sram2_rdata,
  output [5:0]   io_sram3_addr,
  output         io_sram3_cen,
  output         io_sram3_wen,
  output [127:0] io_sram3_wmask,
  output [127:0] io_sram3_wdata,
  input  [127:0] io_sram3_rdata,
  output [5:0]   io_sram4_addr,
  output         io_sram4_cen,
  output         io_sram4_wen,
  output [127:0] io_sram4_wmask,
  output [127:0] io_sram4_wdata,
  input  [127:0] io_sram4_rdata,
  output [5:0]   io_sram5_addr,
  output         io_sram5_cen,
  output         io_sram5_wen,
  output [127:0] io_sram5_wmask,
  output [127:0] io_sram5_wdata,
  input  [127:0] io_sram5_rdata,
  output [5:0]   io_sram6_addr,
  output         io_sram6_cen,
  output         io_sram6_wen,
  output [127:0] io_sram6_wmask,
  output [127:0] io_sram6_wdata,
  input  [127:0] io_sram6_rdata,
  output [5:0]   io_sram7_addr,
  output         io_sram7_cen,
  output         io_sram7_wen,
  output [127:0] io_sram7_wmask,
  output [127:0] io_sram7_wdata,
  input  [127:0] io_sram7_rdata
);
  wire  my_if_clock; // @[MycpuCoreTop.scala 39:32]
  wire  my_if_reset; // @[MycpuCoreTop.scala 39:32]
  wire [31:0] my_if_io_branch_br_target; // @[MycpuCoreTop.scala 39:32]
  wire  my_if_io_branch_br_en; // @[MycpuCoreTop.scala 39:32]
  wire  my_if_io_inst_mem_req_ready; // @[MycpuCoreTop.scala 39:32]
  wire  my_if_io_inst_mem_req_valid; // @[MycpuCoreTop.scala 39:32]
  wire [31:0] my_if_io_inst_mem_req_bits_addr; // @[MycpuCoreTop.scala 39:32]
  wire  my_if_io_inst_mem_req_bits_mthrough; // @[MycpuCoreTop.scala 39:32]
  wire [63:0] my_if_io_inst_mem_ret_rdata; // @[MycpuCoreTop.scala 39:32]
  wire  my_if_io_inst_mem_ret_valid; // @[MycpuCoreTop.scala 39:32]
  wire  my_if_io_if2id_ready; // @[MycpuCoreTop.scala 39:32]
  wire  my_if_io_if2id_valid; // @[MycpuCoreTop.scala 39:32]
  wire [31:0] my_if_io_if2id_bits_inst; // @[MycpuCoreTop.scala 39:32]
  wire [31:0] my_if_io_if2id_bits_pc; // @[MycpuCoreTop.scala 39:32]
  wire  my_if_io_exc_br_exc_br; // @[MycpuCoreTop.scala 39:32]
  wire [31:0] my_if_io_exc_br_exc_target; // @[MycpuCoreTop.scala 39:32]
  wire  my_id_clock; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_reset; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_if2id_ready; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_if2id_valid; // @[MycpuCoreTop.scala 40:32]
  wire [31:0] my_id_io_if2id_bits_inst; // @[MycpuCoreTop.scala 40:32]
  wire [31:0] my_id_io_if2id_bits_pc; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_id2ex_ready; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_id2ex_valid; // @[MycpuCoreTop.scala 40:32]
  wire [22:0] my_id_io_id2ex_bits_alu_op; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_id2ex_bits_src1_sel; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_id2ex_bits_src2_sel; // @[MycpuCoreTop.scala 40:32]
  wire [8:0] my_id_io_id2ex_bits_br_type; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_id2ex_bits_gr_we; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_id2ex_bits_wb_sel; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_id2ex_bits_mem_en; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_id2ex_bits_mem_wr; // @[MycpuCoreTop.scala 40:32]
  wire [6:0] my_id_io_id2ex_bits_mem_type; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_id2ex_bits_rv64w; // @[MycpuCoreTop.scala 40:32]
  wire [2:0] my_id_io_id2ex_bits_ex_sel; // @[MycpuCoreTop.scala 40:32]
  wire [2:0] my_id_io_id2ex_bits_csr_op; // @[MycpuCoreTop.scala 40:32]
  wire [2:0] my_id_io_id2ex_bits_exc_type; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_id2ex_bits_op_muldiv; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_id2ex_bits_is_fencei; // @[MycpuCoreTop.scala 40:32]
  wire [4:0] my_id_io_id2ex_bits_dest; // @[MycpuCoreTop.scala 40:32]
  wire [31:0] my_id_io_id2ex_bits_pc; // @[MycpuCoreTop.scala 40:32]
  wire [63:0] my_id_io_id2ex_bits_rs1; // @[MycpuCoreTop.scala 40:32]
  wire [63:0] my_id_io_id2ex_bits_rs2; // @[MycpuCoreTop.scala 40:32]
  wire [63:0] my_id_io_id2ex_bits_imm; // @[MycpuCoreTop.scala 40:32]
  wire [63:0] my_id_io_id2ex_bits_mem_wdata; // @[MycpuCoreTop.scala 40:32]
  wire [11:0] my_id_io_id2ex_bits_csr_num; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_wb2rf_rf_we; // @[MycpuCoreTop.scala 40:32]
  wire [4:0] my_id_io_wb2rf_waddr; // @[MycpuCoreTop.scala 40:32]
  wire [63:0] my_id_io_wb2rf_wdata; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_exc_flush; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_br_flush; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_es_forward_valid; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_es_forward_bits_en; // @[MycpuCoreTop.scala 40:32]
  wire [4:0] my_id_io_es_forward_bits_dest; // @[MycpuCoreTop.scala 40:32]
  wire [63:0] my_id_io_es_forward_bits_data; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_ms_forward_valid; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_ms_forward_bits_en; // @[MycpuCoreTop.scala 40:32]
  wire [4:0] my_id_io_ms_forward_bits_dest; // @[MycpuCoreTop.scala 40:32]
  wire [63:0] my_id_io_ms_forward_bits_data; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_ws_forward_valid; // @[MycpuCoreTop.scala 40:32]
  wire  my_id_io_ws_forward_bits_en; // @[MycpuCoreTop.scala 40:32]
  wire [4:0] my_id_io_ws_forward_bits_dest; // @[MycpuCoreTop.scala 40:32]
  wire [63:0] my_id_io_ws_forward_bits_data; // @[MycpuCoreTop.scala 40:32]
  wire  my_ex_clock; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_reset; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_id2ex_ready; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_id2ex_valid; // @[MycpuCoreTop.scala 41:32]
  wire [22:0] my_ex_io_id2ex_bits_alu_op; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_id2ex_bits_src1_sel; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_id2ex_bits_src2_sel; // @[MycpuCoreTop.scala 41:32]
  wire [8:0] my_ex_io_id2ex_bits_br_type; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_id2ex_bits_gr_we; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_id2ex_bits_wb_sel; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_id2ex_bits_mem_en; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_id2ex_bits_mem_wr; // @[MycpuCoreTop.scala 41:32]
  wire [6:0] my_ex_io_id2ex_bits_mem_type; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_id2ex_bits_rv64w; // @[MycpuCoreTop.scala 41:32]
  wire [2:0] my_ex_io_id2ex_bits_ex_sel; // @[MycpuCoreTop.scala 41:32]
  wire [2:0] my_ex_io_id2ex_bits_csr_op; // @[MycpuCoreTop.scala 41:32]
  wire [2:0] my_ex_io_id2ex_bits_exc_type; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_id2ex_bits_op_muldiv; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_id2ex_bits_is_fencei; // @[MycpuCoreTop.scala 41:32]
  wire [4:0] my_ex_io_id2ex_bits_dest; // @[MycpuCoreTop.scala 41:32]
  wire [31:0] my_ex_io_id2ex_bits_pc; // @[MycpuCoreTop.scala 41:32]
  wire [63:0] my_ex_io_id2ex_bits_rs1; // @[MycpuCoreTop.scala 41:32]
  wire [63:0] my_ex_io_id2ex_bits_rs2; // @[MycpuCoreTop.scala 41:32]
  wire [63:0] my_ex_io_id2ex_bits_imm; // @[MycpuCoreTop.scala 41:32]
  wire [63:0] my_ex_io_id2ex_bits_mem_wdata; // @[MycpuCoreTop.scala 41:32]
  wire [11:0] my_ex_io_id2ex_bits_csr_num; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_ex2mem_ready; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_ex2mem_valid; // @[MycpuCoreTop.scala 41:32]
  wire [31:0] my_ex_io_ex2mem_bits_pc; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_ex2mem_bits_gr_we; // @[MycpuCoreTop.scala 41:32]
  wire [4:0] my_ex_io_ex2mem_bits_dest; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_ex2mem_bits_wb_sel; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_ex2mem_bits_mem_en; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_ex2mem_bits_mem_wr; // @[MycpuCoreTop.scala 41:32]
  wire [6:0] my_ex_io_ex2mem_bits_mem_type; // @[MycpuCoreTop.scala 41:32]
  wire [2:0] my_ex_io_ex2mem_bits_csr_op; // @[MycpuCoreTop.scala 41:32]
  wire [2:0] my_ex_io_ex2mem_bits_exc_type; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_ex2mem_bits_is_fencei; // @[MycpuCoreTop.scala 41:32]
  wire [63:0] my_ex_io_ex2mem_bits_result; // @[MycpuCoreTop.scala 41:32]
  wire [63:0] my_ex_io_ex2mem_bits_mem_wdata; // @[MycpuCoreTop.scala 41:32]
  wire [11:0] my_ex_io_ex2mem_bits_csr_num; // @[MycpuCoreTop.scala 41:32]
  wire [63:0] my_ex_io_ex2mem_bits_rs1; // @[MycpuCoreTop.scala 41:32]
  wire [31:0] my_ex_io_ex2mem_bits_br_br_target; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_ex2mem_bits_br_br_en; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_exc_flush; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_br_flush; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_es_forward_valid; // @[MycpuCoreTop.scala 41:32]
  wire  my_ex_io_es_forward_bits_en; // @[MycpuCoreTop.scala 41:32]
  wire [4:0] my_ex_io_es_forward_bits_dest; // @[MycpuCoreTop.scala 41:32]
  wire [63:0] my_ex_io_es_forward_bits_data; // @[MycpuCoreTop.scala 41:32]
  wire  my_mem_clock; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_reset; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_ex2mem_ready; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_ex2mem_valid; // @[MycpuCoreTop.scala 42:32]
  wire [31:0] my_mem_io_ex2mem_bits_pc; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_ex2mem_bits_gr_we; // @[MycpuCoreTop.scala 42:32]
  wire [4:0] my_mem_io_ex2mem_bits_dest; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_ex2mem_bits_wb_sel; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_ex2mem_bits_mem_en; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_ex2mem_bits_mem_wr; // @[MycpuCoreTop.scala 42:32]
  wire [6:0] my_mem_io_ex2mem_bits_mem_type; // @[MycpuCoreTop.scala 42:32]
  wire [2:0] my_mem_io_ex2mem_bits_csr_op; // @[MycpuCoreTop.scala 42:32]
  wire [2:0] my_mem_io_ex2mem_bits_exc_type; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_ex2mem_bits_is_fencei; // @[MycpuCoreTop.scala 42:32]
  wire [63:0] my_mem_io_ex2mem_bits_result; // @[MycpuCoreTop.scala 42:32]
  wire [63:0] my_mem_io_ex2mem_bits_mem_wdata; // @[MycpuCoreTop.scala 42:32]
  wire [11:0] my_mem_io_ex2mem_bits_csr_num; // @[MycpuCoreTop.scala 42:32]
  wire [63:0] my_mem_io_ex2mem_bits_rs1; // @[MycpuCoreTop.scala 42:32]
  wire [31:0] my_mem_io_ex2mem_bits_br_br_target; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_ex2mem_bits_br_br_en; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_mem2wb_valid; // @[MycpuCoreTop.scala 42:32]
  wire [31:0] my_mem_io_mem2wb_bits_pc; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_mem2wb_bits_gr_we; // @[MycpuCoreTop.scala 42:32]
  wire [2:0] my_mem_io_mem2wb_bits_csr_op; // @[MycpuCoreTop.scala 42:32]
  wire [2:0] my_mem_io_mem2wb_bits_exc_type; // @[MycpuCoreTop.scala 42:32]
  wire [4:0] my_mem_io_mem2wb_bits_dest; // @[MycpuCoreTop.scala 42:32]
  wire [63:0] my_mem_io_mem2wb_bits_result; // @[MycpuCoreTop.scala 42:32]
  wire [11:0] my_mem_io_mem2wb_bits_csr_num; // @[MycpuCoreTop.scala 42:32]
  wire [63:0] my_mem_io_mem2wb_bits_rs1; // @[MycpuCoreTop.scala 42:32]
  wire [31:0] my_mem_io_branch_br_target; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_branch_br_en; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_exc_flush; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_data_mem_req_ready; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_data_mem_req_valid; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_data_mem_req_bits_wr; // @[MycpuCoreTop.scala 42:32]
  wire [31:0] my_mem_io_data_mem_req_bits_addr; // @[MycpuCoreTop.scala 42:32]
  wire [1:0] my_mem_io_data_mem_req_bits_size; // @[MycpuCoreTop.scala 42:32]
  wire [63:0] my_mem_io_data_mem_req_bits_wdata; // @[MycpuCoreTop.scala 42:32]
  wire [7:0] my_mem_io_data_mem_req_bits_wstrb; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_data_mem_req_bits_mthrough; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_data_mem_req_bits_fencei; // @[MycpuCoreTop.scala 42:32]
  wire [63:0] my_mem_io_data_mem_ret_rdata; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_data_mem_ret_valid; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_ms_forward_valid; // @[MycpuCoreTop.scala 42:32]
  wire  my_mem_io_ms_forward_bits_en; // @[MycpuCoreTop.scala 42:32]
  wire [4:0] my_mem_io_ms_forward_bits_dest; // @[MycpuCoreTop.scala 42:32]
  wire [63:0] my_mem_io_ms_forward_bits_data; // @[MycpuCoreTop.scala 42:32]
  wire  my_wb_clock; // @[MycpuCoreTop.scala 43:32]
  wire  my_wb_reset; // @[MycpuCoreTop.scala 43:32]
  wire  my_wb_io_mem2wb_ready; // @[MycpuCoreTop.scala 43:32]
  wire  my_wb_io_mem2wb_valid; // @[MycpuCoreTop.scala 43:32]
  wire [31:0] my_wb_io_mem2wb_bits_pc; // @[MycpuCoreTop.scala 43:32]
  wire  my_wb_io_mem2wb_bits_gr_we; // @[MycpuCoreTop.scala 43:32]
  wire [2:0] my_wb_io_mem2wb_bits_csr_op; // @[MycpuCoreTop.scala 43:32]
  wire [2:0] my_wb_io_mem2wb_bits_exc_type; // @[MycpuCoreTop.scala 43:32]
  wire [4:0] my_wb_io_mem2wb_bits_dest; // @[MycpuCoreTop.scala 43:32]
  wire [63:0] my_wb_io_mem2wb_bits_result; // @[MycpuCoreTop.scala 43:32]
  wire [11:0] my_wb_io_mem2wb_bits_csr_num; // @[MycpuCoreTop.scala 43:32]
  wire [63:0] my_wb_io_mem2wb_bits_rs1; // @[MycpuCoreTop.scala 43:32]
  wire  my_wb_io_wb2rf_rf_we; // @[MycpuCoreTop.scala 43:32]
  wire [4:0] my_wb_io_wb2rf_waddr; // @[MycpuCoreTop.scala 43:32]
  wire [63:0] my_wb_io_wb2rf_wdata; // @[MycpuCoreTop.scala 43:32]
  wire  my_wb_io_exc_br_exc_br; // @[MycpuCoreTop.scala 43:32]
  wire [31:0] my_wb_io_exc_br_exc_target; // @[MycpuCoreTop.scala 43:32]
  wire  my_wb_io_csr_op_csr_en; // @[MycpuCoreTop.scala 43:32]
  wire [2:0] my_wb_io_csr_op_csr_op; // @[MycpuCoreTop.scala 43:32]
  wire [11:0] my_wb_io_csr_op_csr_num; // @[MycpuCoreTop.scala 43:32]
  wire [63:0] my_wb_io_csr_op_csr_wdata; // @[MycpuCoreTop.scala 43:32]
  wire [63:0] my_wb_io_csr_op_csr_old; // @[MycpuCoreTop.scala 43:32]
  wire  my_wb_io_csr_exc_ecall; // @[MycpuCoreTop.scala 43:32]
  wire  my_wb_io_csr_exc_mret; // @[MycpuCoreTop.scala 43:32]
  wire [29:0] my_wb_io_csr_exc_epc; // @[MycpuCoreTop.scala 43:32]
  wire [63:0] my_wb_io_csr_exc_exc_code; // @[MycpuCoreTop.scala 43:32]
  wire  my_wb_io_csr_exc_intr_t; // @[MycpuCoreTop.scala 43:32]
  wire [31:0] my_wb_io_csr_exc_mret_addr; // @[MycpuCoreTop.scala 43:32]
  wire [31:0] my_wb_io_csr_out_mtvec; // @[MycpuCoreTop.scala 43:32]
  wire  my_wb_io_ws_forward_valid; // @[MycpuCoreTop.scala 43:32]
  wire  my_wb_io_ws_forward_bits_en; // @[MycpuCoreTop.scala 43:32]
  wire [4:0] my_wb_io_ws_forward_bits_dest; // @[MycpuCoreTop.scala 43:32]
  wire [63:0] my_wb_io_ws_forward_bits_data; // @[MycpuCoreTop.scala 43:32]
  wire  my_csr_clock; // @[MycpuCoreTop.scala 44:32]
  wire  my_csr_reset; // @[MycpuCoreTop.scala 44:32]
  wire  my_csr_io_op_csr_en; // @[MycpuCoreTop.scala 44:32]
  wire [2:0] my_csr_io_op_csr_op; // @[MycpuCoreTop.scala 44:32]
  wire [11:0] my_csr_io_op_csr_num; // @[MycpuCoreTop.scala 44:32]
  wire [63:0] my_csr_io_op_csr_wdata; // @[MycpuCoreTop.scala 44:32]
  wire [63:0] my_csr_io_op_csr_old; // @[MycpuCoreTop.scala 44:32]
  wire [31:0] my_csr_io_out_mtvec; // @[MycpuCoreTop.scala 44:32]
  wire  my_csr_io_exc_ecall; // @[MycpuCoreTop.scala 44:32]
  wire  my_csr_io_exc_mret; // @[MycpuCoreTop.scala 44:32]
  wire [29:0] my_csr_io_exc_epc; // @[MycpuCoreTop.scala 44:32]
  wire [63:0] my_csr_io_exc_exc_code; // @[MycpuCoreTop.scala 44:32]
  wire  my_csr_io_exc_intr_t; // @[MycpuCoreTop.scala 44:32]
  wire [31:0] my_csr_io_exc_mret_addr; // @[MycpuCoreTop.scala 44:32]
  wire  my_csr_io_timer_intr; // @[MycpuCoreTop.scala 44:32]
  wire  my_csr_io_external_intr; // @[MycpuCoreTop.scala 44:32]
  wire  my_csr_io_timer_intr_clr; // @[MycpuCoreTop.scala 44:32]
  wire  ysyx_22051110_AXIBridge_clock; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_reset; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_in_req_ready; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_in_req_valid; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_in_req_bits_wr; // @[MycpuCoreTop.scala 45:53]
  wire [31:0] ysyx_22051110_AXIBridge_io_in_req_bits_addr; // @[MycpuCoreTop.scala 45:53]
  wire [1:0] ysyx_22051110_AXIBridge_io_in_req_bits_size; // @[MycpuCoreTop.scala 45:53]
  wire [127:0] ysyx_22051110_AXIBridge_io_in_req_bits_wdata; // @[MycpuCoreTop.scala 45:53]
  wire [7:0] ysyx_22051110_AXIBridge_io_in_req_bits_wstrb; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_in_req_bits_mthrough; // @[MycpuCoreTop.scala 45:53]
  wire [63:0] ysyx_22051110_AXIBridge_io_in_ret_rdata; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_in_ret_valid; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_in_rlast; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_out_ar_ready; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_out_ar_valid; // @[MycpuCoreTop.scala 45:53]
  wire [31:0] ysyx_22051110_AXIBridge_io_out_ar_bits_araddr; // @[MycpuCoreTop.scala 45:53]
  wire [7:0] ysyx_22051110_AXIBridge_io_out_ar_bits_arlen; // @[MycpuCoreTop.scala 45:53]
  wire [2:0] ysyx_22051110_AXIBridge_io_out_ar_bits_arsize; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_out_rd_ready; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_out_rd_valid; // @[MycpuCoreTop.scala 45:53]
  wire [63:0] ysyx_22051110_AXIBridge_io_out_rd_bits_rdata; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_out_rd_bits_rlast; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_out_aw_ready; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_out_aw_valid; // @[MycpuCoreTop.scala 45:53]
  wire [31:0] ysyx_22051110_AXIBridge_io_out_aw_bits_awaddr; // @[MycpuCoreTop.scala 45:53]
  wire [7:0] ysyx_22051110_AXIBridge_io_out_aw_bits_awlen; // @[MycpuCoreTop.scala 45:53]
  wire [2:0] ysyx_22051110_AXIBridge_io_out_aw_bits_awsize; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_out_wt_ready; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_out_wt_valid; // @[MycpuCoreTop.scala 45:53]
  wire [63:0] ysyx_22051110_AXIBridge_io_out_wt_bits_wdata; // @[MycpuCoreTop.scala 45:53]
  wire [7:0] ysyx_22051110_AXIBridge_io_out_wt_bits_wstrb; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_out_wt_bits_wlast; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_out_b_ready; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_io_out_b_valid; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_clock; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_reset; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_in_req_ready; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_in_req_valid; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_in_req_bits_wr; // @[MycpuCoreTop.scala 45:53]
  wire [31:0] ysyx_22051110_AXIBridge_1_io_in_req_bits_addr; // @[MycpuCoreTop.scala 45:53]
  wire [1:0] ysyx_22051110_AXIBridge_1_io_in_req_bits_size; // @[MycpuCoreTop.scala 45:53]
  wire [127:0] ysyx_22051110_AXIBridge_1_io_in_req_bits_wdata; // @[MycpuCoreTop.scala 45:53]
  wire [7:0] ysyx_22051110_AXIBridge_1_io_in_req_bits_wstrb; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_in_req_bits_mthrough; // @[MycpuCoreTop.scala 45:53]
  wire [63:0] ysyx_22051110_AXIBridge_1_io_in_ret_rdata; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_in_ret_valid; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_in_rlast; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_out_ar_ready; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_out_ar_valid; // @[MycpuCoreTop.scala 45:53]
  wire [31:0] ysyx_22051110_AXIBridge_1_io_out_ar_bits_araddr; // @[MycpuCoreTop.scala 45:53]
  wire [7:0] ysyx_22051110_AXIBridge_1_io_out_ar_bits_arlen; // @[MycpuCoreTop.scala 45:53]
  wire [2:0] ysyx_22051110_AXIBridge_1_io_out_ar_bits_arsize; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_out_rd_ready; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_out_rd_valid; // @[MycpuCoreTop.scala 45:53]
  wire [63:0] ysyx_22051110_AXIBridge_1_io_out_rd_bits_rdata; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_out_rd_bits_rlast; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_out_aw_ready; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_out_aw_valid; // @[MycpuCoreTop.scala 45:53]
  wire [31:0] ysyx_22051110_AXIBridge_1_io_out_aw_bits_awaddr; // @[MycpuCoreTop.scala 45:53]
  wire [7:0] ysyx_22051110_AXIBridge_1_io_out_aw_bits_awlen; // @[MycpuCoreTop.scala 45:53]
  wire [2:0] ysyx_22051110_AXIBridge_1_io_out_aw_bits_awsize; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_out_wt_ready; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_out_wt_valid; // @[MycpuCoreTop.scala 45:53]
  wire [63:0] ysyx_22051110_AXIBridge_1_io_out_wt_bits_wdata; // @[MycpuCoreTop.scala 45:53]
  wire [7:0] ysyx_22051110_AXIBridge_1_io_out_wt_bits_wstrb; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_out_wt_bits_wlast; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_out_b_ready; // @[MycpuCoreTop.scala 45:53]
  wire  ysyx_22051110_AXIBridge_1_io_out_b_valid; // @[MycpuCoreTop.scala 45:53]
  wire  my_mmc_io_in_req_ready; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_in_req_valid; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_in_req_bits_wr; // @[MycpuCoreTop.scala 46:32]
  wire [31:0] my_mmc_io_in_req_bits_addr; // @[MycpuCoreTop.scala 46:32]
  wire [1:0] my_mmc_io_in_req_bits_size; // @[MycpuCoreTop.scala 46:32]
  wire [127:0] my_mmc_io_in_req_bits_wdata; // @[MycpuCoreTop.scala 46:32]
  wire [7:0] my_mmc_io_in_req_bits_wstrb; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_in_req_bits_mthrough; // @[MycpuCoreTop.scala 46:32]
  wire [63:0] my_mmc_io_in_ret_rdata; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_in_ret_valid; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_in_rlast; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_clint_out_en; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_clint_out_wr; // @[MycpuCoreTop.scala 46:32]
  wire [31:0] my_mmc_io_clint_out_addr; // @[MycpuCoreTop.scala 46:32]
  wire [63:0] my_mmc_io_clint_out_wdata; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_clint_out_clint_hit; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_clint_out_ret_valid; // @[MycpuCoreTop.scala 46:32]
  wire [63:0] my_mmc_io_clint_out_rdata; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_axi_out_req_ready; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_axi_out_req_valid; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_axi_out_req_bits_wr; // @[MycpuCoreTop.scala 46:32]
  wire [31:0] my_mmc_io_axi_out_req_bits_addr; // @[MycpuCoreTop.scala 46:32]
  wire [1:0] my_mmc_io_axi_out_req_bits_size; // @[MycpuCoreTop.scala 46:32]
  wire [127:0] my_mmc_io_axi_out_req_bits_wdata; // @[MycpuCoreTop.scala 46:32]
  wire [7:0] my_mmc_io_axi_out_req_bits_wstrb; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_axi_out_req_bits_mthrough; // @[MycpuCoreTop.scala 46:32]
  wire [63:0] my_mmc_io_axi_out_ret_rdata; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_axi_out_ret_valid; // @[MycpuCoreTop.scala 46:32]
  wire  my_mmc_io_axi_out_rlast; // @[MycpuCoreTop.scala 46:32]
  wire  my_icache_clock; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_reset; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_in_req_ready; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_in_req_valid; // @[MycpuCoreTop.scala 48:32]
  wire [31:0] my_icache_io_in_req_bits_addr; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_in_req_bits_mthrough; // @[MycpuCoreTop.scala 48:32]
  wire [63:0] my_icache_io_in_ret_rdata; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_in_ret_valid; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_out_req_ready; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_out_req_valid; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_out_req_bits_wr; // @[MycpuCoreTop.scala 48:32]
  wire [31:0] my_icache_io_out_req_bits_addr; // @[MycpuCoreTop.scala 48:32]
  wire [1:0] my_icache_io_out_req_bits_size; // @[MycpuCoreTop.scala 48:32]
  wire [127:0] my_icache_io_out_req_bits_wdata; // @[MycpuCoreTop.scala 48:32]
  wire [7:0] my_icache_io_out_req_bits_wstrb; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_out_req_bits_mthrough; // @[MycpuCoreTop.scala 48:32]
  wire [63:0] my_icache_io_out_ret_rdata; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_out_ret_valid; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_out_rlast; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_flush; // @[MycpuCoreTop.scala 48:32]
  wire [5:0] my_icache_io_cache_data_0_addr; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_cache_data_0_cen; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_cache_data_0_wen; // @[MycpuCoreTop.scala 48:32]
  wire [127:0] my_icache_io_cache_data_0_wdata; // @[MycpuCoreTop.scala 48:32]
  wire [127:0] my_icache_io_cache_data_0_rdata; // @[MycpuCoreTop.scala 48:32]
  wire [5:0] my_icache_io_cache_data_1_addr; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_cache_data_1_cen; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_cache_data_1_wen; // @[MycpuCoreTop.scala 48:32]
  wire [127:0] my_icache_io_cache_data_1_wdata; // @[MycpuCoreTop.scala 48:32]
  wire [127:0] my_icache_io_cache_data_1_rdata; // @[MycpuCoreTop.scala 48:32]
  wire [5:0] my_icache_io_cache_data_2_addr; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_cache_data_2_cen; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_cache_data_2_wen; // @[MycpuCoreTop.scala 48:32]
  wire [127:0] my_icache_io_cache_data_2_wdata; // @[MycpuCoreTop.scala 48:32]
  wire [127:0] my_icache_io_cache_data_2_rdata; // @[MycpuCoreTop.scala 48:32]
  wire [5:0] my_icache_io_cache_data_3_addr; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_cache_data_3_cen; // @[MycpuCoreTop.scala 48:32]
  wire  my_icache_io_cache_data_3_wen; // @[MycpuCoreTop.scala 48:32]
  wire [127:0] my_icache_io_cache_data_3_wdata; // @[MycpuCoreTop.scala 48:32]
  wire [127:0] my_icache_io_cache_data_3_rdata; // @[MycpuCoreTop.scala 48:32]
  wire  my_dcache_clock; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_reset; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_in_req_ready; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_in_req_valid; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_in_req_bits_wr; // @[MycpuCoreTop.scala 50:32]
  wire [31:0] my_dcache_io_in_req_bits_addr; // @[MycpuCoreTop.scala 50:32]
  wire [1:0] my_dcache_io_in_req_bits_size; // @[MycpuCoreTop.scala 50:32]
  wire [63:0] my_dcache_io_in_req_bits_wdata; // @[MycpuCoreTop.scala 50:32]
  wire [7:0] my_dcache_io_in_req_bits_wstrb; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_in_req_bits_mthrough; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_in_req_bits_fencei; // @[MycpuCoreTop.scala 50:32]
  wire [63:0] my_dcache_io_in_ret_rdata; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_in_ret_valid; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_out_req_ready; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_out_req_valid; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_out_req_bits_wr; // @[MycpuCoreTop.scala 50:32]
  wire [31:0] my_dcache_io_out_req_bits_addr; // @[MycpuCoreTop.scala 50:32]
  wire [1:0] my_dcache_io_out_req_bits_size; // @[MycpuCoreTop.scala 50:32]
  wire [127:0] my_dcache_io_out_req_bits_wdata; // @[MycpuCoreTop.scala 50:32]
  wire [7:0] my_dcache_io_out_req_bits_wstrb; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_out_req_bits_mthrough; // @[MycpuCoreTop.scala 50:32]
  wire [63:0] my_dcache_io_out_ret_rdata; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_out_ret_valid; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_out_rlast; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_flush; // @[MycpuCoreTop.scala 50:32]
  wire [5:0] my_dcache_io_cache_data_0_addr; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_cache_data_0_cen; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_cache_data_0_wen; // @[MycpuCoreTop.scala 50:32]
  wire [127:0] my_dcache_io_cache_data_0_wdata; // @[MycpuCoreTop.scala 50:32]
  wire [127:0] my_dcache_io_cache_data_0_rdata; // @[MycpuCoreTop.scala 50:32]
  wire [5:0] my_dcache_io_cache_data_1_addr; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_cache_data_1_cen; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_cache_data_1_wen; // @[MycpuCoreTop.scala 50:32]
  wire [127:0] my_dcache_io_cache_data_1_wdata; // @[MycpuCoreTop.scala 50:32]
  wire [127:0] my_dcache_io_cache_data_1_rdata; // @[MycpuCoreTop.scala 50:32]
  wire [5:0] my_dcache_io_cache_data_2_addr; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_cache_data_2_cen; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_cache_data_2_wen; // @[MycpuCoreTop.scala 50:32]
  wire [127:0] my_dcache_io_cache_data_2_wdata; // @[MycpuCoreTop.scala 50:32]
  wire [127:0] my_dcache_io_cache_data_2_rdata; // @[MycpuCoreTop.scala 50:32]
  wire [5:0] my_dcache_io_cache_data_3_addr; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_cache_data_3_cen; // @[MycpuCoreTop.scala 50:32]
  wire  my_dcache_io_cache_data_3_wen; // @[MycpuCoreTop.scala 50:32]
  wire [127:0] my_dcache_io_cache_data_3_wdata; // @[MycpuCoreTop.scala 50:32]
  wire [127:0] my_dcache_io_cache_data_3_rdata; // @[MycpuCoreTop.scala 50:32]
  wire  my_clint_clock; // @[MycpuCoreTop.scala 52:32]
  wire  my_clint_reset; // @[MycpuCoreTop.scala 52:32]
  wire  my_clint_io_in_en; // @[MycpuCoreTop.scala 52:32]
  wire  my_clint_io_in_wr; // @[MycpuCoreTop.scala 52:32]
  wire [31:0] my_clint_io_in_addr; // @[MycpuCoreTop.scala 52:32]
  wire [63:0] my_clint_io_in_wdata; // @[MycpuCoreTop.scala 52:32]
  wire  my_clint_io_in_clint_hit; // @[MycpuCoreTop.scala 52:32]
  wire  my_clint_io_in_ret_valid; // @[MycpuCoreTop.scala 52:32]
  wire [63:0] my_clint_io_in_rdata; // @[MycpuCoreTop.scala 52:32]
  wire  my_clint_io_has_intr_t; // @[MycpuCoreTop.scala 52:32]
  wire  my_clint_io_clr_intr_t; // @[MycpuCoreTop.scala 52:32]
  wire  my_arbiter_clock; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_reset; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_0_ar_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_0_ar_valid; // @[MycpuCoreTop.scala 53:31]
  wire [31:0] my_arbiter_io_in_0_ar_bits_araddr; // @[MycpuCoreTop.scala 53:31]
  wire [7:0] my_arbiter_io_in_0_ar_bits_arlen; // @[MycpuCoreTop.scala 53:31]
  wire [2:0] my_arbiter_io_in_0_ar_bits_arsize; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_0_rd_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_0_rd_valid; // @[MycpuCoreTop.scala 53:31]
  wire [63:0] my_arbiter_io_in_0_rd_bits_rdata; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_0_rd_bits_rlast; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_0_aw_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_0_aw_valid; // @[MycpuCoreTop.scala 53:31]
  wire [31:0] my_arbiter_io_in_0_aw_bits_awaddr; // @[MycpuCoreTop.scala 53:31]
  wire [7:0] my_arbiter_io_in_0_aw_bits_awlen; // @[MycpuCoreTop.scala 53:31]
  wire [2:0] my_arbiter_io_in_0_aw_bits_awsize; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_0_wt_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_0_wt_valid; // @[MycpuCoreTop.scala 53:31]
  wire [63:0] my_arbiter_io_in_0_wt_bits_wdata; // @[MycpuCoreTop.scala 53:31]
  wire [7:0] my_arbiter_io_in_0_wt_bits_wstrb; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_0_wt_bits_wlast; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_0_b_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_0_b_valid; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_1_ar_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_1_ar_valid; // @[MycpuCoreTop.scala 53:31]
  wire [31:0] my_arbiter_io_in_1_ar_bits_araddr; // @[MycpuCoreTop.scala 53:31]
  wire [7:0] my_arbiter_io_in_1_ar_bits_arlen; // @[MycpuCoreTop.scala 53:31]
  wire [2:0] my_arbiter_io_in_1_ar_bits_arsize; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_1_rd_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_1_rd_valid; // @[MycpuCoreTop.scala 53:31]
  wire [63:0] my_arbiter_io_in_1_rd_bits_rdata; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_1_rd_bits_rlast; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_1_aw_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_1_aw_valid; // @[MycpuCoreTop.scala 53:31]
  wire [31:0] my_arbiter_io_in_1_aw_bits_awaddr; // @[MycpuCoreTop.scala 53:31]
  wire [7:0] my_arbiter_io_in_1_aw_bits_awlen; // @[MycpuCoreTop.scala 53:31]
  wire [2:0] my_arbiter_io_in_1_aw_bits_awsize; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_1_wt_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_1_wt_valid; // @[MycpuCoreTop.scala 53:31]
  wire [63:0] my_arbiter_io_in_1_wt_bits_wdata; // @[MycpuCoreTop.scala 53:31]
  wire [7:0] my_arbiter_io_in_1_wt_bits_wstrb; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_1_wt_bits_wlast; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_1_b_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_in_1_b_valid; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_out_ar_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_out_ar_valid; // @[MycpuCoreTop.scala 53:31]
  wire [31:0] my_arbiter_io_out_ar_bits_araddr; // @[MycpuCoreTop.scala 53:31]
  wire [7:0] my_arbiter_io_out_ar_bits_arlen; // @[MycpuCoreTop.scala 53:31]
  wire [2:0] my_arbiter_io_out_ar_bits_arsize; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_out_rd_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_out_rd_valid; // @[MycpuCoreTop.scala 53:31]
  wire [63:0] my_arbiter_io_out_rd_bits_rdata; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_out_rd_bits_rlast; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_out_aw_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_out_aw_valid; // @[MycpuCoreTop.scala 53:31]
  wire [31:0] my_arbiter_io_out_aw_bits_awaddr; // @[MycpuCoreTop.scala 53:31]
  wire [7:0] my_arbiter_io_out_aw_bits_awlen; // @[MycpuCoreTop.scala 53:31]
  wire [2:0] my_arbiter_io_out_aw_bits_awsize; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_out_wt_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_out_wt_valid; // @[MycpuCoreTop.scala 53:31]
  wire [63:0] my_arbiter_io_out_wt_bits_wdata; // @[MycpuCoreTop.scala 53:31]
  wire [7:0] my_arbiter_io_out_wt_bits_wstrb; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_out_wt_bits_wlast; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_out_b_ready; // @[MycpuCoreTop.scala 53:31]
  wire  my_arbiter_io_out_b_valid; // @[MycpuCoreTop.scala 53:31]
  ysyx_22051110_If_stage my_if ( // @[MycpuCoreTop.scala 39:32]
    .clock(my_if_clock),
    .reset(my_if_reset),
    .io_branch_br_target(my_if_io_branch_br_target),
    .io_branch_br_en(my_if_io_branch_br_en),
    .io_inst_mem_req_ready(my_if_io_inst_mem_req_ready),
    .io_inst_mem_req_valid(my_if_io_inst_mem_req_valid),
    .io_inst_mem_req_bits_addr(my_if_io_inst_mem_req_bits_addr),
    .io_inst_mem_req_bits_mthrough(my_if_io_inst_mem_req_bits_mthrough),
    .io_inst_mem_ret_rdata(my_if_io_inst_mem_ret_rdata),
    .io_inst_mem_ret_valid(my_if_io_inst_mem_ret_valid),
    .io_if2id_ready(my_if_io_if2id_ready),
    .io_if2id_valid(my_if_io_if2id_valid),
    .io_if2id_bits_inst(my_if_io_if2id_bits_inst),
    .io_if2id_bits_pc(my_if_io_if2id_bits_pc),
    .io_exc_br_exc_br(my_if_io_exc_br_exc_br),
    .io_exc_br_exc_target(my_if_io_exc_br_exc_target)
  );
  ysyx_22051110_Id_stage my_id ( // @[MycpuCoreTop.scala 40:32]
    .clock(my_id_clock),
    .reset(my_id_reset),
    .io_if2id_ready(my_id_io_if2id_ready),
    .io_if2id_valid(my_id_io_if2id_valid),
    .io_if2id_bits_inst(my_id_io_if2id_bits_inst),
    .io_if2id_bits_pc(my_id_io_if2id_bits_pc),
    .io_id2ex_ready(my_id_io_id2ex_ready),
    .io_id2ex_valid(my_id_io_id2ex_valid),
    .io_id2ex_bits_alu_op(my_id_io_id2ex_bits_alu_op),
    .io_id2ex_bits_src1_sel(my_id_io_id2ex_bits_src1_sel),
    .io_id2ex_bits_src2_sel(my_id_io_id2ex_bits_src2_sel),
    .io_id2ex_bits_br_type(my_id_io_id2ex_bits_br_type),
    .io_id2ex_bits_gr_we(my_id_io_id2ex_bits_gr_we),
    .io_id2ex_bits_wb_sel(my_id_io_id2ex_bits_wb_sel),
    .io_id2ex_bits_mem_en(my_id_io_id2ex_bits_mem_en),
    .io_id2ex_bits_mem_wr(my_id_io_id2ex_bits_mem_wr),
    .io_id2ex_bits_mem_type(my_id_io_id2ex_bits_mem_type),
    .io_id2ex_bits_rv64w(my_id_io_id2ex_bits_rv64w),
    .io_id2ex_bits_ex_sel(my_id_io_id2ex_bits_ex_sel),
    .io_id2ex_bits_csr_op(my_id_io_id2ex_bits_csr_op),
    .io_id2ex_bits_exc_type(my_id_io_id2ex_bits_exc_type),
    .io_id2ex_bits_op_muldiv(my_id_io_id2ex_bits_op_muldiv),
    .io_id2ex_bits_is_fencei(my_id_io_id2ex_bits_is_fencei),
    .io_id2ex_bits_dest(my_id_io_id2ex_bits_dest),
    .io_id2ex_bits_pc(my_id_io_id2ex_bits_pc),
    .io_id2ex_bits_rs1(my_id_io_id2ex_bits_rs1),
    .io_id2ex_bits_rs2(my_id_io_id2ex_bits_rs2),
    .io_id2ex_bits_imm(my_id_io_id2ex_bits_imm),
    .io_id2ex_bits_mem_wdata(my_id_io_id2ex_bits_mem_wdata),
    .io_id2ex_bits_csr_num(my_id_io_id2ex_bits_csr_num),
    .io_wb2rf_rf_we(my_id_io_wb2rf_rf_we),
    .io_wb2rf_waddr(my_id_io_wb2rf_waddr),
    .io_wb2rf_wdata(my_id_io_wb2rf_wdata),
    .io_exc_flush(my_id_io_exc_flush),
    .io_br_flush(my_id_io_br_flush),
    .io_es_forward_valid(my_id_io_es_forward_valid),
    .io_es_forward_bits_en(my_id_io_es_forward_bits_en),
    .io_es_forward_bits_dest(my_id_io_es_forward_bits_dest),
    .io_es_forward_bits_data(my_id_io_es_forward_bits_data),
    .io_ms_forward_valid(my_id_io_ms_forward_valid),
    .io_ms_forward_bits_en(my_id_io_ms_forward_bits_en),
    .io_ms_forward_bits_dest(my_id_io_ms_forward_bits_dest),
    .io_ms_forward_bits_data(my_id_io_ms_forward_bits_data),
    .io_ws_forward_valid(my_id_io_ws_forward_valid),
    .io_ws_forward_bits_en(my_id_io_ws_forward_bits_en),
    .io_ws_forward_bits_dest(my_id_io_ws_forward_bits_dest),
    .io_ws_forward_bits_data(my_id_io_ws_forward_bits_data)
  );
  ysyx_22051110_Ex_stage my_ex ( // @[MycpuCoreTop.scala 41:32]
    .clock(my_ex_clock),
    .reset(my_ex_reset),
    .io_id2ex_ready(my_ex_io_id2ex_ready),
    .io_id2ex_valid(my_ex_io_id2ex_valid),
    .io_id2ex_bits_alu_op(my_ex_io_id2ex_bits_alu_op),
    .io_id2ex_bits_src1_sel(my_ex_io_id2ex_bits_src1_sel),
    .io_id2ex_bits_src2_sel(my_ex_io_id2ex_bits_src2_sel),
    .io_id2ex_bits_br_type(my_ex_io_id2ex_bits_br_type),
    .io_id2ex_bits_gr_we(my_ex_io_id2ex_bits_gr_we),
    .io_id2ex_bits_wb_sel(my_ex_io_id2ex_bits_wb_sel),
    .io_id2ex_bits_mem_en(my_ex_io_id2ex_bits_mem_en),
    .io_id2ex_bits_mem_wr(my_ex_io_id2ex_bits_mem_wr),
    .io_id2ex_bits_mem_type(my_ex_io_id2ex_bits_mem_type),
    .io_id2ex_bits_rv64w(my_ex_io_id2ex_bits_rv64w),
    .io_id2ex_bits_ex_sel(my_ex_io_id2ex_bits_ex_sel),
    .io_id2ex_bits_csr_op(my_ex_io_id2ex_bits_csr_op),
    .io_id2ex_bits_exc_type(my_ex_io_id2ex_bits_exc_type),
    .io_id2ex_bits_op_muldiv(my_ex_io_id2ex_bits_op_muldiv),
    .io_id2ex_bits_is_fencei(my_ex_io_id2ex_bits_is_fencei),
    .io_id2ex_bits_dest(my_ex_io_id2ex_bits_dest),
    .io_id2ex_bits_pc(my_ex_io_id2ex_bits_pc),
    .io_id2ex_bits_rs1(my_ex_io_id2ex_bits_rs1),
    .io_id2ex_bits_rs2(my_ex_io_id2ex_bits_rs2),
    .io_id2ex_bits_imm(my_ex_io_id2ex_bits_imm),
    .io_id2ex_bits_mem_wdata(my_ex_io_id2ex_bits_mem_wdata),
    .io_id2ex_bits_csr_num(my_ex_io_id2ex_bits_csr_num),
    .io_ex2mem_ready(my_ex_io_ex2mem_ready),
    .io_ex2mem_valid(my_ex_io_ex2mem_valid),
    .io_ex2mem_bits_pc(my_ex_io_ex2mem_bits_pc),
    .io_ex2mem_bits_gr_we(my_ex_io_ex2mem_bits_gr_we),
    .io_ex2mem_bits_dest(my_ex_io_ex2mem_bits_dest),
    .io_ex2mem_bits_wb_sel(my_ex_io_ex2mem_bits_wb_sel),
    .io_ex2mem_bits_mem_en(my_ex_io_ex2mem_bits_mem_en),
    .io_ex2mem_bits_mem_wr(my_ex_io_ex2mem_bits_mem_wr),
    .io_ex2mem_bits_mem_type(my_ex_io_ex2mem_bits_mem_type),
    .io_ex2mem_bits_csr_op(my_ex_io_ex2mem_bits_csr_op),
    .io_ex2mem_bits_exc_type(my_ex_io_ex2mem_bits_exc_type),
    .io_ex2mem_bits_is_fencei(my_ex_io_ex2mem_bits_is_fencei),
    .io_ex2mem_bits_result(my_ex_io_ex2mem_bits_result),
    .io_ex2mem_bits_mem_wdata(my_ex_io_ex2mem_bits_mem_wdata),
    .io_ex2mem_bits_csr_num(my_ex_io_ex2mem_bits_csr_num),
    .io_ex2mem_bits_rs1(my_ex_io_ex2mem_bits_rs1),
    .io_ex2mem_bits_br_br_target(my_ex_io_ex2mem_bits_br_br_target),
    .io_ex2mem_bits_br_br_en(my_ex_io_ex2mem_bits_br_br_en),
    .io_exc_flush(my_ex_io_exc_flush),
    .io_br_flush(my_ex_io_br_flush),
    .io_es_forward_valid(my_ex_io_es_forward_valid),
    .io_es_forward_bits_en(my_ex_io_es_forward_bits_en),
    .io_es_forward_bits_dest(my_ex_io_es_forward_bits_dest),
    .io_es_forward_bits_data(my_ex_io_es_forward_bits_data)
  );
  ysyx_22051110_Mem_stage my_mem ( // @[MycpuCoreTop.scala 42:32]
    .clock(my_mem_clock),
    .reset(my_mem_reset),
    .io_ex2mem_ready(my_mem_io_ex2mem_ready),
    .io_ex2mem_valid(my_mem_io_ex2mem_valid),
    .io_ex2mem_bits_pc(my_mem_io_ex2mem_bits_pc),
    .io_ex2mem_bits_gr_we(my_mem_io_ex2mem_bits_gr_we),
    .io_ex2mem_bits_dest(my_mem_io_ex2mem_bits_dest),
    .io_ex2mem_bits_wb_sel(my_mem_io_ex2mem_bits_wb_sel),
    .io_ex2mem_bits_mem_en(my_mem_io_ex2mem_bits_mem_en),
    .io_ex2mem_bits_mem_wr(my_mem_io_ex2mem_bits_mem_wr),
    .io_ex2mem_bits_mem_type(my_mem_io_ex2mem_bits_mem_type),
    .io_ex2mem_bits_csr_op(my_mem_io_ex2mem_bits_csr_op),
    .io_ex2mem_bits_exc_type(my_mem_io_ex2mem_bits_exc_type),
    .io_ex2mem_bits_is_fencei(my_mem_io_ex2mem_bits_is_fencei),
    .io_ex2mem_bits_result(my_mem_io_ex2mem_bits_result),
    .io_ex2mem_bits_mem_wdata(my_mem_io_ex2mem_bits_mem_wdata),
    .io_ex2mem_bits_csr_num(my_mem_io_ex2mem_bits_csr_num),
    .io_ex2mem_bits_rs1(my_mem_io_ex2mem_bits_rs1),
    .io_ex2mem_bits_br_br_target(my_mem_io_ex2mem_bits_br_br_target),
    .io_ex2mem_bits_br_br_en(my_mem_io_ex2mem_bits_br_br_en),
    .io_mem2wb_valid(my_mem_io_mem2wb_valid),
    .io_mem2wb_bits_pc(my_mem_io_mem2wb_bits_pc),
    .io_mem2wb_bits_gr_we(my_mem_io_mem2wb_bits_gr_we),
    .io_mem2wb_bits_csr_op(my_mem_io_mem2wb_bits_csr_op),
    .io_mem2wb_bits_exc_type(my_mem_io_mem2wb_bits_exc_type),
    .io_mem2wb_bits_dest(my_mem_io_mem2wb_bits_dest),
    .io_mem2wb_bits_result(my_mem_io_mem2wb_bits_result),
    .io_mem2wb_bits_csr_num(my_mem_io_mem2wb_bits_csr_num),
    .io_mem2wb_bits_rs1(my_mem_io_mem2wb_bits_rs1),
    .io_branch_br_target(my_mem_io_branch_br_target),
    .io_branch_br_en(my_mem_io_branch_br_en),
    .io_exc_flush(my_mem_io_exc_flush),
    .io_data_mem_req_ready(my_mem_io_data_mem_req_ready),
    .io_data_mem_req_valid(my_mem_io_data_mem_req_valid),
    .io_data_mem_req_bits_wr(my_mem_io_data_mem_req_bits_wr),
    .io_data_mem_req_bits_addr(my_mem_io_data_mem_req_bits_addr),
    .io_data_mem_req_bits_size(my_mem_io_data_mem_req_bits_size),
    .io_data_mem_req_bits_wdata(my_mem_io_data_mem_req_bits_wdata),
    .io_data_mem_req_bits_wstrb(my_mem_io_data_mem_req_bits_wstrb),
    .io_data_mem_req_bits_mthrough(my_mem_io_data_mem_req_bits_mthrough),
    .io_data_mem_req_bits_fencei(my_mem_io_data_mem_req_bits_fencei),
    .io_data_mem_ret_rdata(my_mem_io_data_mem_ret_rdata),
    .io_data_mem_ret_valid(my_mem_io_data_mem_ret_valid),
    .io_ms_forward_valid(my_mem_io_ms_forward_valid),
    .io_ms_forward_bits_en(my_mem_io_ms_forward_bits_en),
    .io_ms_forward_bits_dest(my_mem_io_ms_forward_bits_dest),
    .io_ms_forward_bits_data(my_mem_io_ms_forward_bits_data)
  );
  ysyx_22051110_Wb_stage my_wb ( // @[MycpuCoreTop.scala 43:32]
    .clock(my_wb_clock),
    .reset(my_wb_reset),
    .io_mem2wb_ready(my_wb_io_mem2wb_ready),
    .io_mem2wb_valid(my_wb_io_mem2wb_valid),
    .io_mem2wb_bits_pc(my_wb_io_mem2wb_bits_pc),
    .io_mem2wb_bits_gr_we(my_wb_io_mem2wb_bits_gr_we),
    .io_mem2wb_bits_csr_op(my_wb_io_mem2wb_bits_csr_op),
    .io_mem2wb_bits_exc_type(my_wb_io_mem2wb_bits_exc_type),
    .io_mem2wb_bits_dest(my_wb_io_mem2wb_bits_dest),
    .io_mem2wb_bits_result(my_wb_io_mem2wb_bits_result),
    .io_mem2wb_bits_csr_num(my_wb_io_mem2wb_bits_csr_num),
    .io_mem2wb_bits_rs1(my_wb_io_mem2wb_bits_rs1),
    .io_wb2rf_rf_we(my_wb_io_wb2rf_rf_we),
    .io_wb2rf_waddr(my_wb_io_wb2rf_waddr),
    .io_wb2rf_wdata(my_wb_io_wb2rf_wdata),
    .io_exc_br_exc_br(my_wb_io_exc_br_exc_br),
    .io_exc_br_exc_target(my_wb_io_exc_br_exc_target),
    .io_csr_op_csr_en(my_wb_io_csr_op_csr_en),
    .io_csr_op_csr_op(my_wb_io_csr_op_csr_op),
    .io_csr_op_csr_num(my_wb_io_csr_op_csr_num),
    .io_csr_op_csr_wdata(my_wb_io_csr_op_csr_wdata),
    .io_csr_op_csr_old(my_wb_io_csr_op_csr_old),
    .io_csr_exc_ecall(my_wb_io_csr_exc_ecall),
    .io_csr_exc_mret(my_wb_io_csr_exc_mret),
    .io_csr_exc_epc(my_wb_io_csr_exc_epc),
    .io_csr_exc_exc_code(my_wb_io_csr_exc_exc_code),
    .io_csr_exc_intr_t(my_wb_io_csr_exc_intr_t),
    .io_csr_exc_mret_addr(my_wb_io_csr_exc_mret_addr),
    .io_csr_out_mtvec(my_wb_io_csr_out_mtvec),
    .io_ws_forward_valid(my_wb_io_ws_forward_valid),
    .io_ws_forward_bits_en(my_wb_io_ws_forward_bits_en),
    .io_ws_forward_bits_dest(my_wb_io_ws_forward_bits_dest),
    .io_ws_forward_bits_data(my_wb_io_ws_forward_bits_data)
  );
  ysyx_22051110_Csr my_csr ( // @[MycpuCoreTop.scala 44:32]
    .clock(my_csr_clock),
    .reset(my_csr_reset),
    .io_op_csr_en(my_csr_io_op_csr_en),
    .io_op_csr_op(my_csr_io_op_csr_op),
    .io_op_csr_num(my_csr_io_op_csr_num),
    .io_op_csr_wdata(my_csr_io_op_csr_wdata),
    .io_op_csr_old(my_csr_io_op_csr_old),
    .io_out_mtvec(my_csr_io_out_mtvec),
    .io_exc_ecall(my_csr_io_exc_ecall),
    .io_exc_mret(my_csr_io_exc_mret),
    .io_exc_epc(my_csr_io_exc_epc),
    .io_exc_exc_code(my_csr_io_exc_exc_code),
    .io_exc_intr_t(my_csr_io_exc_intr_t),
    .io_exc_mret_addr(my_csr_io_exc_mret_addr),
    .io_timer_intr(my_csr_io_timer_intr),
    .io_external_intr(my_csr_io_external_intr),
    .io_timer_intr_clr(my_csr_io_timer_intr_clr)
  );
  ysyx_22051110_AXIBridge ysyx_22051110_AXIBridge ( // @[MycpuCoreTop.scala 45:53]
    .clock(ysyx_22051110_AXIBridge_clock),
    .reset(ysyx_22051110_AXIBridge_reset),
    .io_in_req_ready(ysyx_22051110_AXIBridge_io_in_req_ready),
    .io_in_req_valid(ysyx_22051110_AXIBridge_io_in_req_valid),
    .io_in_req_bits_wr(ysyx_22051110_AXIBridge_io_in_req_bits_wr),
    .io_in_req_bits_addr(ysyx_22051110_AXIBridge_io_in_req_bits_addr),
    .io_in_req_bits_size(ysyx_22051110_AXIBridge_io_in_req_bits_size),
    .io_in_req_bits_wdata(ysyx_22051110_AXIBridge_io_in_req_bits_wdata),
    .io_in_req_bits_wstrb(ysyx_22051110_AXIBridge_io_in_req_bits_wstrb),
    .io_in_req_bits_mthrough(ysyx_22051110_AXIBridge_io_in_req_bits_mthrough),
    .io_in_ret_rdata(ysyx_22051110_AXIBridge_io_in_ret_rdata),
    .io_in_ret_valid(ysyx_22051110_AXIBridge_io_in_ret_valid),
    .io_in_rlast(ysyx_22051110_AXIBridge_io_in_rlast),
    .io_out_ar_ready(ysyx_22051110_AXIBridge_io_out_ar_ready),
    .io_out_ar_valid(ysyx_22051110_AXIBridge_io_out_ar_valid),
    .io_out_ar_bits_araddr(ysyx_22051110_AXIBridge_io_out_ar_bits_araddr),
    .io_out_ar_bits_arlen(ysyx_22051110_AXIBridge_io_out_ar_bits_arlen),
    .io_out_ar_bits_arsize(ysyx_22051110_AXIBridge_io_out_ar_bits_arsize),
    .io_out_rd_ready(ysyx_22051110_AXIBridge_io_out_rd_ready),
    .io_out_rd_valid(ysyx_22051110_AXIBridge_io_out_rd_valid),
    .io_out_rd_bits_rdata(ysyx_22051110_AXIBridge_io_out_rd_bits_rdata),
    .io_out_rd_bits_rlast(ysyx_22051110_AXIBridge_io_out_rd_bits_rlast),
    .io_out_aw_ready(ysyx_22051110_AXIBridge_io_out_aw_ready),
    .io_out_aw_valid(ysyx_22051110_AXIBridge_io_out_aw_valid),
    .io_out_aw_bits_awaddr(ysyx_22051110_AXIBridge_io_out_aw_bits_awaddr),
    .io_out_aw_bits_awlen(ysyx_22051110_AXIBridge_io_out_aw_bits_awlen),
    .io_out_aw_bits_awsize(ysyx_22051110_AXIBridge_io_out_aw_bits_awsize),
    .io_out_wt_ready(ysyx_22051110_AXIBridge_io_out_wt_ready),
    .io_out_wt_valid(ysyx_22051110_AXIBridge_io_out_wt_valid),
    .io_out_wt_bits_wdata(ysyx_22051110_AXIBridge_io_out_wt_bits_wdata),
    .io_out_wt_bits_wstrb(ysyx_22051110_AXIBridge_io_out_wt_bits_wstrb),
    .io_out_wt_bits_wlast(ysyx_22051110_AXIBridge_io_out_wt_bits_wlast),
    .io_out_b_ready(ysyx_22051110_AXIBridge_io_out_b_ready),
    .io_out_b_valid(ysyx_22051110_AXIBridge_io_out_b_valid)
  );
  ysyx_22051110_AXIBridge ysyx_22051110_AXIBridge_1 ( // @[MycpuCoreTop.scala 45:53]
    .clock(ysyx_22051110_AXIBridge_1_clock),
    .reset(ysyx_22051110_AXIBridge_1_reset),
    .io_in_req_ready(ysyx_22051110_AXIBridge_1_io_in_req_ready),
    .io_in_req_valid(ysyx_22051110_AXIBridge_1_io_in_req_valid),
    .io_in_req_bits_wr(ysyx_22051110_AXIBridge_1_io_in_req_bits_wr),
    .io_in_req_bits_addr(ysyx_22051110_AXIBridge_1_io_in_req_bits_addr),
    .io_in_req_bits_size(ysyx_22051110_AXIBridge_1_io_in_req_bits_size),
    .io_in_req_bits_wdata(ysyx_22051110_AXIBridge_1_io_in_req_bits_wdata),
    .io_in_req_bits_wstrb(ysyx_22051110_AXIBridge_1_io_in_req_bits_wstrb),
    .io_in_req_bits_mthrough(ysyx_22051110_AXIBridge_1_io_in_req_bits_mthrough),
    .io_in_ret_rdata(ysyx_22051110_AXIBridge_1_io_in_ret_rdata),
    .io_in_ret_valid(ysyx_22051110_AXIBridge_1_io_in_ret_valid),
    .io_in_rlast(ysyx_22051110_AXIBridge_1_io_in_rlast),
    .io_out_ar_ready(ysyx_22051110_AXIBridge_1_io_out_ar_ready),
    .io_out_ar_valid(ysyx_22051110_AXIBridge_1_io_out_ar_valid),
    .io_out_ar_bits_araddr(ysyx_22051110_AXIBridge_1_io_out_ar_bits_araddr),
    .io_out_ar_bits_arlen(ysyx_22051110_AXIBridge_1_io_out_ar_bits_arlen),
    .io_out_ar_bits_arsize(ysyx_22051110_AXIBridge_1_io_out_ar_bits_arsize),
    .io_out_rd_ready(ysyx_22051110_AXIBridge_1_io_out_rd_ready),
    .io_out_rd_valid(ysyx_22051110_AXIBridge_1_io_out_rd_valid),
    .io_out_rd_bits_rdata(ysyx_22051110_AXIBridge_1_io_out_rd_bits_rdata),
    .io_out_rd_bits_rlast(ysyx_22051110_AXIBridge_1_io_out_rd_bits_rlast),
    .io_out_aw_ready(ysyx_22051110_AXIBridge_1_io_out_aw_ready),
    .io_out_aw_valid(ysyx_22051110_AXIBridge_1_io_out_aw_valid),
    .io_out_aw_bits_awaddr(ysyx_22051110_AXIBridge_1_io_out_aw_bits_awaddr),
    .io_out_aw_bits_awlen(ysyx_22051110_AXIBridge_1_io_out_aw_bits_awlen),
    .io_out_aw_bits_awsize(ysyx_22051110_AXIBridge_1_io_out_aw_bits_awsize),
    .io_out_wt_ready(ysyx_22051110_AXIBridge_1_io_out_wt_ready),
    .io_out_wt_valid(ysyx_22051110_AXIBridge_1_io_out_wt_valid),
    .io_out_wt_bits_wdata(ysyx_22051110_AXIBridge_1_io_out_wt_bits_wdata),
    .io_out_wt_bits_wstrb(ysyx_22051110_AXIBridge_1_io_out_wt_bits_wstrb),
    .io_out_wt_bits_wlast(ysyx_22051110_AXIBridge_1_io_out_wt_bits_wlast),
    .io_out_b_ready(ysyx_22051110_AXIBridge_1_io_out_b_ready),
    .io_out_b_valid(ysyx_22051110_AXIBridge_1_io_out_b_valid)
  );
  ysyx_22051110_MemoryController my_mmc ( // @[MycpuCoreTop.scala 46:32]
    .io_in_req_ready(my_mmc_io_in_req_ready),
    .io_in_req_valid(my_mmc_io_in_req_valid),
    .io_in_req_bits_wr(my_mmc_io_in_req_bits_wr),
    .io_in_req_bits_addr(my_mmc_io_in_req_bits_addr),
    .io_in_req_bits_size(my_mmc_io_in_req_bits_size),
    .io_in_req_bits_wdata(my_mmc_io_in_req_bits_wdata),
    .io_in_req_bits_wstrb(my_mmc_io_in_req_bits_wstrb),
    .io_in_req_bits_mthrough(my_mmc_io_in_req_bits_mthrough),
    .io_in_ret_rdata(my_mmc_io_in_ret_rdata),
    .io_in_ret_valid(my_mmc_io_in_ret_valid),
    .io_in_rlast(my_mmc_io_in_rlast),
    .io_clint_out_en(my_mmc_io_clint_out_en),
    .io_clint_out_wr(my_mmc_io_clint_out_wr),
    .io_clint_out_addr(my_mmc_io_clint_out_addr),
    .io_clint_out_wdata(my_mmc_io_clint_out_wdata),
    .io_clint_out_clint_hit(my_mmc_io_clint_out_clint_hit),
    .io_clint_out_ret_valid(my_mmc_io_clint_out_ret_valid),
    .io_clint_out_rdata(my_mmc_io_clint_out_rdata),
    .io_axi_out_req_ready(my_mmc_io_axi_out_req_ready),
    .io_axi_out_req_valid(my_mmc_io_axi_out_req_valid),
    .io_axi_out_req_bits_wr(my_mmc_io_axi_out_req_bits_wr),
    .io_axi_out_req_bits_addr(my_mmc_io_axi_out_req_bits_addr),
    .io_axi_out_req_bits_size(my_mmc_io_axi_out_req_bits_size),
    .io_axi_out_req_bits_wdata(my_mmc_io_axi_out_req_bits_wdata),
    .io_axi_out_req_bits_wstrb(my_mmc_io_axi_out_req_bits_wstrb),
    .io_axi_out_req_bits_mthrough(my_mmc_io_axi_out_req_bits_mthrough),
    .io_axi_out_ret_rdata(my_mmc_io_axi_out_ret_rdata),
    .io_axi_out_ret_valid(my_mmc_io_axi_out_ret_valid),
    .io_axi_out_rlast(my_mmc_io_axi_out_rlast)
  );
  ysyx_22051110_CacheTop my_icache ( // @[MycpuCoreTop.scala 48:32]
    .clock(my_icache_clock),
    .reset(my_icache_reset),
    .io_in_req_ready(my_icache_io_in_req_ready),
    .io_in_req_valid(my_icache_io_in_req_valid),
    .io_in_req_bits_addr(my_icache_io_in_req_bits_addr),
    .io_in_req_bits_mthrough(my_icache_io_in_req_bits_mthrough),
    .io_in_ret_rdata(my_icache_io_in_ret_rdata),
    .io_in_ret_valid(my_icache_io_in_ret_valid),
    .io_out_req_ready(my_icache_io_out_req_ready),
    .io_out_req_valid(my_icache_io_out_req_valid),
    .io_out_req_bits_wr(my_icache_io_out_req_bits_wr),
    .io_out_req_bits_addr(my_icache_io_out_req_bits_addr),
    .io_out_req_bits_size(my_icache_io_out_req_bits_size),
    .io_out_req_bits_wdata(my_icache_io_out_req_bits_wdata),
    .io_out_req_bits_wstrb(my_icache_io_out_req_bits_wstrb),
    .io_out_req_bits_mthrough(my_icache_io_out_req_bits_mthrough),
    .io_out_ret_rdata(my_icache_io_out_ret_rdata),
    .io_out_ret_valid(my_icache_io_out_ret_valid),
    .io_out_rlast(my_icache_io_out_rlast),
    .io_flush(my_icache_io_flush),
    .io_cache_data_0_addr(my_icache_io_cache_data_0_addr),
    .io_cache_data_0_cen(my_icache_io_cache_data_0_cen),
    .io_cache_data_0_wen(my_icache_io_cache_data_0_wen),
    .io_cache_data_0_wdata(my_icache_io_cache_data_0_wdata),
    .io_cache_data_0_rdata(my_icache_io_cache_data_0_rdata),
    .io_cache_data_1_addr(my_icache_io_cache_data_1_addr),
    .io_cache_data_1_cen(my_icache_io_cache_data_1_cen),
    .io_cache_data_1_wen(my_icache_io_cache_data_1_wen),
    .io_cache_data_1_wdata(my_icache_io_cache_data_1_wdata),
    .io_cache_data_1_rdata(my_icache_io_cache_data_1_rdata),
    .io_cache_data_2_addr(my_icache_io_cache_data_2_addr),
    .io_cache_data_2_cen(my_icache_io_cache_data_2_cen),
    .io_cache_data_2_wen(my_icache_io_cache_data_2_wen),
    .io_cache_data_2_wdata(my_icache_io_cache_data_2_wdata),
    .io_cache_data_2_rdata(my_icache_io_cache_data_2_rdata),
    .io_cache_data_3_addr(my_icache_io_cache_data_3_addr),
    .io_cache_data_3_cen(my_icache_io_cache_data_3_cen),
    .io_cache_data_3_wen(my_icache_io_cache_data_3_wen),
    .io_cache_data_3_wdata(my_icache_io_cache_data_3_wdata),
    .io_cache_data_3_rdata(my_icache_io_cache_data_3_rdata)
  );
  ysyx_22051110_CacheTop_1 my_dcache ( // @[MycpuCoreTop.scala 50:32]
    .clock(my_dcache_clock),
    .reset(my_dcache_reset),
    .io_in_req_ready(my_dcache_io_in_req_ready),
    .io_in_req_valid(my_dcache_io_in_req_valid),
    .io_in_req_bits_wr(my_dcache_io_in_req_bits_wr),
    .io_in_req_bits_addr(my_dcache_io_in_req_bits_addr),
    .io_in_req_bits_size(my_dcache_io_in_req_bits_size),
    .io_in_req_bits_wdata(my_dcache_io_in_req_bits_wdata),
    .io_in_req_bits_wstrb(my_dcache_io_in_req_bits_wstrb),
    .io_in_req_bits_mthrough(my_dcache_io_in_req_bits_mthrough),
    .io_in_req_bits_fencei(my_dcache_io_in_req_bits_fencei),
    .io_in_ret_rdata(my_dcache_io_in_ret_rdata),
    .io_in_ret_valid(my_dcache_io_in_ret_valid),
    .io_out_req_ready(my_dcache_io_out_req_ready),
    .io_out_req_valid(my_dcache_io_out_req_valid),
    .io_out_req_bits_wr(my_dcache_io_out_req_bits_wr),
    .io_out_req_bits_addr(my_dcache_io_out_req_bits_addr),
    .io_out_req_bits_size(my_dcache_io_out_req_bits_size),
    .io_out_req_bits_wdata(my_dcache_io_out_req_bits_wdata),
    .io_out_req_bits_wstrb(my_dcache_io_out_req_bits_wstrb),
    .io_out_req_bits_mthrough(my_dcache_io_out_req_bits_mthrough),
    .io_out_ret_rdata(my_dcache_io_out_ret_rdata),
    .io_out_ret_valid(my_dcache_io_out_ret_valid),
    .io_out_rlast(my_dcache_io_out_rlast),
    .io_flush(my_dcache_io_flush),
    .io_cache_data_0_addr(my_dcache_io_cache_data_0_addr),
    .io_cache_data_0_cen(my_dcache_io_cache_data_0_cen),
    .io_cache_data_0_wen(my_dcache_io_cache_data_0_wen),
    .io_cache_data_0_wdata(my_dcache_io_cache_data_0_wdata),
    .io_cache_data_0_rdata(my_dcache_io_cache_data_0_rdata),
    .io_cache_data_1_addr(my_dcache_io_cache_data_1_addr),
    .io_cache_data_1_cen(my_dcache_io_cache_data_1_cen),
    .io_cache_data_1_wen(my_dcache_io_cache_data_1_wen),
    .io_cache_data_1_wdata(my_dcache_io_cache_data_1_wdata),
    .io_cache_data_1_rdata(my_dcache_io_cache_data_1_rdata),
    .io_cache_data_2_addr(my_dcache_io_cache_data_2_addr),
    .io_cache_data_2_cen(my_dcache_io_cache_data_2_cen),
    .io_cache_data_2_wen(my_dcache_io_cache_data_2_wen),
    .io_cache_data_2_wdata(my_dcache_io_cache_data_2_wdata),
    .io_cache_data_2_rdata(my_dcache_io_cache_data_2_rdata),
    .io_cache_data_3_addr(my_dcache_io_cache_data_3_addr),
    .io_cache_data_3_cen(my_dcache_io_cache_data_3_cen),
    .io_cache_data_3_wen(my_dcache_io_cache_data_3_wen),
    .io_cache_data_3_wdata(my_dcache_io_cache_data_3_wdata),
    .io_cache_data_3_rdata(my_dcache_io_cache_data_3_rdata)
  );
  ysyx_22051110_Clint my_clint ( // @[MycpuCoreTop.scala 52:32]
    .clock(my_clint_clock),
    .reset(my_clint_reset),
    .io_in_en(my_clint_io_in_en),
    .io_in_wr(my_clint_io_in_wr),
    .io_in_addr(my_clint_io_in_addr),
    .io_in_wdata(my_clint_io_in_wdata),
    .io_in_clint_hit(my_clint_io_in_clint_hit),
    .io_in_ret_valid(my_clint_io_in_ret_valid),
    .io_in_rdata(my_clint_io_in_rdata),
    .io_has_intr_t(my_clint_io_has_intr_t),
    .io_clr_intr_t(my_clint_io_clr_intr_t)
  );
  ysyx_22051110_AXIArbiter my_arbiter ( // @[MycpuCoreTop.scala 53:31]
    .clock(my_arbiter_clock),
    .reset(my_arbiter_reset),
    .io_in_0_ar_ready(my_arbiter_io_in_0_ar_ready),
    .io_in_0_ar_valid(my_arbiter_io_in_0_ar_valid),
    .io_in_0_ar_bits_araddr(my_arbiter_io_in_0_ar_bits_araddr),
    .io_in_0_ar_bits_arlen(my_arbiter_io_in_0_ar_bits_arlen),
    .io_in_0_ar_bits_arsize(my_arbiter_io_in_0_ar_bits_arsize),
    .io_in_0_rd_ready(my_arbiter_io_in_0_rd_ready),
    .io_in_0_rd_valid(my_arbiter_io_in_0_rd_valid),
    .io_in_0_rd_bits_rdata(my_arbiter_io_in_0_rd_bits_rdata),
    .io_in_0_rd_bits_rlast(my_arbiter_io_in_0_rd_bits_rlast),
    .io_in_0_aw_ready(my_arbiter_io_in_0_aw_ready),
    .io_in_0_aw_valid(my_arbiter_io_in_0_aw_valid),
    .io_in_0_aw_bits_awaddr(my_arbiter_io_in_0_aw_bits_awaddr),
    .io_in_0_aw_bits_awlen(my_arbiter_io_in_0_aw_bits_awlen),
    .io_in_0_aw_bits_awsize(my_arbiter_io_in_0_aw_bits_awsize),
    .io_in_0_wt_ready(my_arbiter_io_in_0_wt_ready),
    .io_in_0_wt_valid(my_arbiter_io_in_0_wt_valid),
    .io_in_0_wt_bits_wdata(my_arbiter_io_in_0_wt_bits_wdata),
    .io_in_0_wt_bits_wstrb(my_arbiter_io_in_0_wt_bits_wstrb),
    .io_in_0_wt_bits_wlast(my_arbiter_io_in_0_wt_bits_wlast),
    .io_in_0_b_ready(my_arbiter_io_in_0_b_ready),
    .io_in_0_b_valid(my_arbiter_io_in_0_b_valid),
    .io_in_1_ar_ready(my_arbiter_io_in_1_ar_ready),
    .io_in_1_ar_valid(my_arbiter_io_in_1_ar_valid),
    .io_in_1_ar_bits_araddr(my_arbiter_io_in_1_ar_bits_araddr),
    .io_in_1_ar_bits_arlen(my_arbiter_io_in_1_ar_bits_arlen),
    .io_in_1_ar_bits_arsize(my_arbiter_io_in_1_ar_bits_arsize),
    .io_in_1_rd_ready(my_arbiter_io_in_1_rd_ready),
    .io_in_1_rd_valid(my_arbiter_io_in_1_rd_valid),
    .io_in_1_rd_bits_rdata(my_arbiter_io_in_1_rd_bits_rdata),
    .io_in_1_rd_bits_rlast(my_arbiter_io_in_1_rd_bits_rlast),
    .io_in_1_aw_ready(my_arbiter_io_in_1_aw_ready),
    .io_in_1_aw_valid(my_arbiter_io_in_1_aw_valid),
    .io_in_1_aw_bits_awaddr(my_arbiter_io_in_1_aw_bits_awaddr),
    .io_in_1_aw_bits_awlen(my_arbiter_io_in_1_aw_bits_awlen),
    .io_in_1_aw_bits_awsize(my_arbiter_io_in_1_aw_bits_awsize),
    .io_in_1_wt_ready(my_arbiter_io_in_1_wt_ready),
    .io_in_1_wt_valid(my_arbiter_io_in_1_wt_valid),
    .io_in_1_wt_bits_wdata(my_arbiter_io_in_1_wt_bits_wdata),
    .io_in_1_wt_bits_wstrb(my_arbiter_io_in_1_wt_bits_wstrb),
    .io_in_1_wt_bits_wlast(my_arbiter_io_in_1_wt_bits_wlast),
    .io_in_1_b_ready(my_arbiter_io_in_1_b_ready),
    .io_in_1_b_valid(my_arbiter_io_in_1_b_valid),
    .io_out_ar_ready(my_arbiter_io_out_ar_ready),
    .io_out_ar_valid(my_arbiter_io_out_ar_valid),
    .io_out_ar_bits_araddr(my_arbiter_io_out_ar_bits_araddr),
    .io_out_ar_bits_arlen(my_arbiter_io_out_ar_bits_arlen),
    .io_out_ar_bits_arsize(my_arbiter_io_out_ar_bits_arsize),
    .io_out_rd_ready(my_arbiter_io_out_rd_ready),
    .io_out_rd_valid(my_arbiter_io_out_rd_valid),
    .io_out_rd_bits_rdata(my_arbiter_io_out_rd_bits_rdata),
    .io_out_rd_bits_rlast(my_arbiter_io_out_rd_bits_rlast),
    .io_out_aw_ready(my_arbiter_io_out_aw_ready),
    .io_out_aw_valid(my_arbiter_io_out_aw_valid),
    .io_out_aw_bits_awaddr(my_arbiter_io_out_aw_bits_awaddr),
    .io_out_aw_bits_awlen(my_arbiter_io_out_aw_bits_awlen),
    .io_out_aw_bits_awsize(my_arbiter_io_out_aw_bits_awsize),
    .io_out_wt_ready(my_arbiter_io_out_wt_ready),
    .io_out_wt_valid(my_arbiter_io_out_wt_valid),
    .io_out_wt_bits_wdata(my_arbiter_io_out_wt_bits_wdata),
    .io_out_wt_bits_wstrb(my_arbiter_io_out_wt_bits_wstrb),
    .io_out_wt_bits_wlast(my_arbiter_io_out_wt_bits_wlast),
    .io_out_b_ready(my_arbiter_io_out_b_ready),
    .io_out_b_valid(my_arbiter_io_out_b_valid)
  );
  assign io_master_awvalid = my_arbiter_io_out_aw_valid; // @[MycpuCoreTop.scala 111:23]
  assign io_master_awid = 4'h0; // @[MycpuCoreTop.scala 112:23]
  assign io_master_awaddr = my_arbiter_io_out_aw_bits_awaddr; // @[MycpuCoreTop.scala 113:58]
  assign io_master_awlen = my_arbiter_io_out_aw_bits_awlen; // @[MycpuCoreTop.scala 114:23]
  assign io_master_awsize = my_arbiter_io_out_aw_bits_awsize; // @[MycpuCoreTop.scala 115:23]
  assign io_master_awburst = 2'h2; // @[MycpuCoreTop.scala 116:23]
  assign io_master_wvalid = my_arbiter_io_out_wt_valid; // @[MycpuCoreTop.scala 119:22]
  assign io_master_wdata = my_arbiter_io_out_wt_bits_wdata; // @[MycpuCoreTop.scala 120:21]
  assign io_master_wstrb = my_arbiter_io_out_wt_bits_wstrb; // @[MycpuCoreTop.scala 121:21]
  assign io_master_wlast = my_arbiter_io_out_wt_bits_wlast; // @[MycpuCoreTop.scala 122:21]
  assign io_master_bready = my_arbiter_io_out_b_ready; // @[MycpuCoreTop.scala 124:22]
  assign io_master_arvalid = my_arbiter_io_out_ar_valid; // @[MycpuCoreTop.scala 130:23]
  assign io_master_arid = 4'h0; // @[MycpuCoreTop.scala 131:23]
  assign io_master_araddr = my_arbiter_io_out_ar_bits_araddr; // @[MycpuCoreTop.scala 132:58]
  assign io_master_arlen = my_arbiter_io_out_ar_bits_arlen; // @[MycpuCoreTop.scala 133:23]
  assign io_master_arsize = my_arbiter_io_out_ar_bits_arsize; // @[MycpuCoreTop.scala 134:23]
  assign io_master_arburst = 2'h2; // @[MycpuCoreTop.scala 135:23]
  assign io_master_rready = my_arbiter_io_out_rd_ready; // @[MycpuCoreTop.scala 137:22]
  assign io_slave_awready = 1'h0; // @[MycpuCoreTop.scala 98:22]
  assign io_slave_wready = 1'h0; // @[MycpuCoreTop.scala 99:22]
  assign io_slave_bvalid = 1'h0; // @[MycpuCoreTop.scala 100:22]
  assign io_slave_bid = 4'h0; // @[MycpuCoreTop.scala 102:22]
  assign io_slave_bresp = 2'h0; // @[MycpuCoreTop.scala 101:22]
  assign io_slave_arready = 1'h0; // @[MycpuCoreTop.scala 103:22]
  assign io_slave_rvalid = 1'h0; // @[MycpuCoreTop.scala 104:22]
  assign io_slave_rid = 4'h0; // @[MycpuCoreTop.scala 108:22]
  assign io_slave_rresp = 2'h0; // @[MycpuCoreTop.scala 105:22]
  assign io_slave_rdata = 64'h0; // @[MycpuCoreTop.scala 106:22]
  assign io_slave_rlast = 1'h0; // @[MycpuCoreTop.scala 107:22]
  assign io_sram0_addr = my_icache_io_cache_data_0_addr; // @[MycpuCoreTop.scala 145:20]
  assign io_sram0_cen = my_icache_io_cache_data_0_cen; // @[MycpuCoreTop.scala 146:20]
  assign io_sram0_wen = my_icache_io_cache_data_0_wen; // @[MycpuCoreTop.scala 147:20]
  assign io_sram0_wmask = 128'h0; // @[MycpuCoreTop.scala 149:20]
  assign io_sram0_wdata = my_icache_io_cache_data_0_wdata; // @[MycpuCoreTop.scala 148:20]
  assign io_sram1_addr = my_icache_io_cache_data_1_addr; // @[MycpuCoreTop.scala 152:20]
  assign io_sram1_cen = my_icache_io_cache_data_1_cen; // @[MycpuCoreTop.scala 153:20]
  assign io_sram1_wen = my_icache_io_cache_data_1_wen; // @[MycpuCoreTop.scala 154:20]
  assign io_sram1_wmask = 128'h0; // @[MycpuCoreTop.scala 156:20]
  assign io_sram1_wdata = my_icache_io_cache_data_1_wdata; // @[MycpuCoreTop.scala 155:20]
  assign io_sram2_addr = my_icache_io_cache_data_2_addr; // @[MycpuCoreTop.scala 159:20]
  assign io_sram2_cen = my_icache_io_cache_data_2_cen; // @[MycpuCoreTop.scala 160:20]
  assign io_sram2_wen = my_icache_io_cache_data_2_wen; // @[MycpuCoreTop.scala 161:20]
  assign io_sram2_wmask = 128'h0; // @[MycpuCoreTop.scala 163:20]
  assign io_sram2_wdata = my_icache_io_cache_data_2_wdata; // @[MycpuCoreTop.scala 162:20]
  assign io_sram3_addr = my_icache_io_cache_data_3_addr; // @[MycpuCoreTop.scala 166:20]
  assign io_sram3_cen = my_icache_io_cache_data_3_cen; // @[MycpuCoreTop.scala 167:20]
  assign io_sram3_wen = my_icache_io_cache_data_3_wen; // @[MycpuCoreTop.scala 168:20]
  assign io_sram3_wmask = 128'h0; // @[MycpuCoreTop.scala 170:20]
  assign io_sram3_wdata = my_icache_io_cache_data_3_wdata; // @[MycpuCoreTop.scala 169:20]
  assign io_sram4_addr = my_dcache_io_cache_data_0_addr; // @[MycpuCoreTop.scala 173:20]
  assign io_sram4_cen = my_dcache_io_cache_data_0_cen; // @[MycpuCoreTop.scala 174:20]
  assign io_sram4_wen = my_dcache_io_cache_data_0_wen; // @[MycpuCoreTop.scala 175:20]
  assign io_sram4_wmask = 128'h0; // @[MycpuCoreTop.scala 177:20]
  assign io_sram4_wdata = my_dcache_io_cache_data_0_wdata; // @[MycpuCoreTop.scala 176:20]
  assign io_sram5_addr = my_dcache_io_cache_data_1_addr; // @[MycpuCoreTop.scala 180:20]
  assign io_sram5_cen = my_dcache_io_cache_data_1_cen; // @[MycpuCoreTop.scala 181:20]
  assign io_sram5_wen = my_dcache_io_cache_data_1_wen; // @[MycpuCoreTop.scala 182:20]
  assign io_sram5_wmask = 128'h0; // @[MycpuCoreTop.scala 184:20]
  assign io_sram5_wdata = my_dcache_io_cache_data_1_wdata; // @[MycpuCoreTop.scala 183:20]
  assign io_sram6_addr = my_dcache_io_cache_data_2_addr; // @[MycpuCoreTop.scala 187:20]
  assign io_sram6_cen = my_dcache_io_cache_data_2_cen; // @[MycpuCoreTop.scala 188:20]
  assign io_sram6_wen = my_dcache_io_cache_data_2_wen; // @[MycpuCoreTop.scala 189:20]
  assign io_sram6_wmask = 128'h0; // @[MycpuCoreTop.scala 191:20]
  assign io_sram6_wdata = my_dcache_io_cache_data_2_wdata; // @[MycpuCoreTop.scala 190:20]
  assign io_sram7_addr = my_dcache_io_cache_data_3_addr; // @[MycpuCoreTop.scala 194:20]
  assign io_sram7_cen = my_dcache_io_cache_data_3_cen; // @[MycpuCoreTop.scala 195:20]
  assign io_sram7_wen = my_dcache_io_cache_data_3_wen; // @[MycpuCoreTop.scala 196:20]
  assign io_sram7_wmask = 128'h0; // @[MycpuCoreTop.scala 198:20]
  assign io_sram7_wdata = my_dcache_io_cache_data_3_wdata; // @[MycpuCoreTop.scala 197:20]
  assign my_if_clock = clock;
  assign my_if_reset = reset;
  assign my_if_io_branch_br_target = my_mem_io_branch_br_target; // @[MycpuCoreTop.scala 56:28]
  assign my_if_io_branch_br_en = my_mem_io_branch_br_en; // @[MycpuCoreTop.scala 56:28]
  assign my_if_io_inst_mem_req_ready = my_icache_io_in_req_ready; // @[MycpuCoreTop.scala 84:28]
  assign my_if_io_inst_mem_ret_rdata = my_icache_io_in_ret_rdata; // @[MycpuCoreTop.scala 84:28]
  assign my_if_io_inst_mem_ret_valid = my_icache_io_in_ret_valid; // @[MycpuCoreTop.scala 84:28]
  assign my_if_io_if2id_ready = my_id_io_if2id_ready; // @[MycpuCoreTop.scala 59:28]
  assign my_if_io_exc_br_exc_br = my_wb_io_exc_br_exc_br; // @[MycpuCoreTop.scala 57:28]
  assign my_if_io_exc_br_exc_target = my_wb_io_exc_br_exc_target; // @[MycpuCoreTop.scala 57:28]
  assign my_id_clock = clock;
  assign my_id_reset = reset;
  assign my_id_io_if2id_valid = my_if_io_if2id_valid; // @[MycpuCoreTop.scala 59:28]
  assign my_id_io_if2id_bits_inst = my_if_io_if2id_bits_inst; // @[MycpuCoreTop.scala 59:28]
  assign my_id_io_if2id_bits_pc = my_if_io_if2id_bits_pc; // @[MycpuCoreTop.scala 59:28]
  assign my_id_io_id2ex_ready = my_ex_io_id2ex_ready; // @[MycpuCoreTop.scala 67:28]
  assign my_id_io_wb2rf_rf_we = my_wb_io_wb2rf_rf_we; // @[MycpuCoreTop.scala 60:28]
  assign my_id_io_wb2rf_waddr = my_wb_io_wb2rf_waddr; // @[MycpuCoreTop.scala 60:28]
  assign my_id_io_wb2rf_wdata = my_wb_io_wb2rf_wdata; // @[MycpuCoreTop.scala 60:28]
  assign my_id_io_exc_flush = my_wb_io_exc_br_exc_br; // @[MycpuCoreTop.scala 61:28]
  assign my_id_io_br_flush = my_mem_io_branch_br_en; // @[MycpuCoreTop.scala 62:28]
  assign my_id_io_es_forward_valid = my_ex_io_es_forward_valid; // @[MycpuCoreTop.scala 63:28]
  assign my_id_io_es_forward_bits_en = my_ex_io_es_forward_bits_en; // @[MycpuCoreTop.scala 63:28]
  assign my_id_io_es_forward_bits_dest = my_ex_io_es_forward_bits_dest; // @[MycpuCoreTop.scala 63:28]
  assign my_id_io_es_forward_bits_data = my_ex_io_es_forward_bits_data; // @[MycpuCoreTop.scala 63:28]
  assign my_id_io_ms_forward_valid = my_mem_io_ms_forward_valid; // @[MycpuCoreTop.scala 64:28]
  assign my_id_io_ms_forward_bits_en = my_mem_io_ms_forward_bits_en; // @[MycpuCoreTop.scala 64:28]
  assign my_id_io_ms_forward_bits_dest = my_mem_io_ms_forward_bits_dest; // @[MycpuCoreTop.scala 64:28]
  assign my_id_io_ms_forward_bits_data = my_mem_io_ms_forward_bits_data; // @[MycpuCoreTop.scala 64:28]
  assign my_id_io_ws_forward_valid = my_wb_io_ws_forward_valid; // @[MycpuCoreTop.scala 65:28]
  assign my_id_io_ws_forward_bits_en = my_wb_io_ws_forward_bits_en; // @[MycpuCoreTop.scala 65:28]
  assign my_id_io_ws_forward_bits_dest = my_wb_io_ws_forward_bits_dest; // @[MycpuCoreTop.scala 65:28]
  assign my_id_io_ws_forward_bits_data = my_wb_io_ws_forward_bits_data; // @[MycpuCoreTop.scala 65:28]
  assign my_ex_clock = clock;
  assign my_ex_reset = reset;
  assign my_ex_io_id2ex_valid = my_id_io_id2ex_valid; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_alu_op = my_id_io_id2ex_bits_alu_op; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_src1_sel = my_id_io_id2ex_bits_src1_sel; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_src2_sel = my_id_io_id2ex_bits_src2_sel; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_br_type = my_id_io_id2ex_bits_br_type; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_gr_we = my_id_io_id2ex_bits_gr_we; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_wb_sel = my_id_io_id2ex_bits_wb_sel; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_mem_en = my_id_io_id2ex_bits_mem_en; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_mem_wr = my_id_io_id2ex_bits_mem_wr; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_mem_type = my_id_io_id2ex_bits_mem_type; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_rv64w = my_id_io_id2ex_bits_rv64w; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_ex_sel = my_id_io_id2ex_bits_ex_sel; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_csr_op = my_id_io_id2ex_bits_csr_op; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_exc_type = my_id_io_id2ex_bits_exc_type; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_op_muldiv = my_id_io_id2ex_bits_op_muldiv; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_is_fencei = my_id_io_id2ex_bits_is_fencei; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_dest = my_id_io_id2ex_bits_dest; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_pc = my_id_io_id2ex_bits_pc; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_rs1 = my_id_io_id2ex_bits_rs1; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_rs2 = my_id_io_id2ex_bits_rs2; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_imm = my_id_io_id2ex_bits_imm; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_mem_wdata = my_id_io_id2ex_bits_mem_wdata; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_id2ex_bits_csr_num = my_id_io_id2ex_bits_csr_num; // @[MycpuCoreTop.scala 67:28]
  assign my_ex_io_ex2mem_ready = my_mem_io_ex2mem_ready; // @[MycpuCoreTop.scala 71:28]
  assign my_ex_io_exc_flush = my_wb_io_exc_br_exc_br; // @[MycpuCoreTop.scala 68:28]
  assign my_ex_io_br_flush = my_mem_io_branch_br_en; // @[MycpuCoreTop.scala 69:28]
  assign my_mem_clock = clock;
  assign my_mem_reset = reset;
  assign my_mem_io_ex2mem_valid = my_ex_io_ex2mem_valid; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_pc = my_ex_io_ex2mem_bits_pc; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_gr_we = my_ex_io_ex2mem_bits_gr_we; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_dest = my_ex_io_ex2mem_bits_dest; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_wb_sel = my_ex_io_ex2mem_bits_wb_sel; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_mem_en = my_ex_io_ex2mem_bits_mem_en; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_mem_wr = my_ex_io_ex2mem_bits_mem_wr; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_mem_type = my_ex_io_ex2mem_bits_mem_type; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_csr_op = my_ex_io_ex2mem_bits_csr_op; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_exc_type = my_ex_io_ex2mem_bits_exc_type; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_is_fencei = my_ex_io_ex2mem_bits_is_fencei; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_result = my_ex_io_ex2mem_bits_result; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_mem_wdata = my_ex_io_ex2mem_bits_mem_wdata; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_csr_num = my_ex_io_ex2mem_bits_csr_num; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_rs1 = my_ex_io_ex2mem_bits_rs1; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_br_br_target = my_ex_io_ex2mem_bits_br_br_target; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_ex2mem_bits_br_br_en = my_ex_io_ex2mem_bits_br_br_en; // @[MycpuCoreTop.scala 71:28]
  assign my_mem_io_exc_flush = my_wb_io_exc_br_exc_br; // @[MycpuCoreTop.scala 72:28]
  assign my_mem_io_data_mem_req_ready = my_dcache_io_in_req_ready; // @[MycpuCoreTop.scala 87:28]
  assign my_mem_io_data_mem_ret_rdata = my_dcache_io_in_ret_rdata; // @[MycpuCoreTop.scala 87:28]
  assign my_mem_io_data_mem_ret_valid = my_dcache_io_in_ret_valid; // @[MycpuCoreTop.scala 87:28]
  assign my_wb_clock = clock;
  assign my_wb_reset = reset;
  assign my_wb_io_mem2wb_valid = my_mem_io_mem2wb_valid; // @[MycpuCoreTop.scala 74:28]
  assign my_wb_io_mem2wb_bits_pc = my_mem_io_mem2wb_bits_pc; // @[MycpuCoreTop.scala 74:28]
  assign my_wb_io_mem2wb_bits_gr_we = my_mem_io_mem2wb_bits_gr_we; // @[MycpuCoreTop.scala 74:28]
  assign my_wb_io_mem2wb_bits_csr_op = my_mem_io_mem2wb_bits_csr_op; // @[MycpuCoreTop.scala 74:28]
  assign my_wb_io_mem2wb_bits_exc_type = my_mem_io_mem2wb_bits_exc_type; // @[MycpuCoreTop.scala 74:28]
  assign my_wb_io_mem2wb_bits_dest = my_mem_io_mem2wb_bits_dest; // @[MycpuCoreTop.scala 74:28]
  assign my_wb_io_mem2wb_bits_result = my_mem_io_mem2wb_bits_result; // @[MycpuCoreTop.scala 74:28]
  assign my_wb_io_mem2wb_bits_csr_num = my_mem_io_mem2wb_bits_csr_num; // @[MycpuCoreTop.scala 74:28]
  assign my_wb_io_mem2wb_bits_rs1 = my_mem_io_mem2wb_bits_rs1; // @[MycpuCoreTop.scala 74:28]
  assign my_wb_io_csr_op_csr_old = my_csr_io_op_csr_old; // @[MycpuCoreTop.scala 76:28]
  assign my_wb_io_csr_exc_intr_t = my_csr_io_exc_intr_t; // @[MycpuCoreTop.scala 77:28]
  assign my_wb_io_csr_exc_mret_addr = my_csr_io_exc_mret_addr; // @[MycpuCoreTop.scala 77:28]
  assign my_wb_io_csr_out_mtvec = my_csr_io_out_mtvec; // @[MycpuCoreTop.scala 78:28]
  assign my_csr_clock = clock;
  assign my_csr_reset = reset;
  assign my_csr_io_op_csr_en = my_wb_io_csr_op_csr_en; // @[MycpuCoreTop.scala 76:28]
  assign my_csr_io_op_csr_op = my_wb_io_csr_op_csr_op; // @[MycpuCoreTop.scala 76:28]
  assign my_csr_io_op_csr_num = my_wb_io_csr_op_csr_num; // @[MycpuCoreTop.scala 76:28]
  assign my_csr_io_op_csr_wdata = my_wb_io_csr_op_csr_wdata; // @[MycpuCoreTop.scala 76:28]
  assign my_csr_io_exc_ecall = my_wb_io_csr_exc_ecall; // @[MycpuCoreTop.scala 77:28]
  assign my_csr_io_exc_mret = my_wb_io_csr_exc_mret; // @[MycpuCoreTop.scala 77:28]
  assign my_csr_io_exc_epc = my_wb_io_csr_exc_epc; // @[MycpuCoreTop.scala 77:28]
  assign my_csr_io_exc_exc_code = my_wb_io_csr_exc_exc_code; // @[MycpuCoreTop.scala 77:28]
  assign my_csr_io_timer_intr = my_clint_io_has_intr_t; // @[MycpuCoreTop.scala 79:30]
  assign my_csr_io_external_intr = io_interrupt; // @[MycpuCoreTop.scala 80:30]
  assign my_csr_io_timer_intr_clr = my_clint_io_clr_intr_t; // @[MycpuCoreTop.scala 81:30]
  assign ysyx_22051110_AXIBridge_clock = clock;
  assign ysyx_22051110_AXIBridge_reset = reset;
  assign ysyx_22051110_AXIBridge_io_in_req_valid = my_icache_io_out_req_valid; // @[MycpuCoreTop.scala 85:28]
  assign ysyx_22051110_AXIBridge_io_in_req_bits_wr = my_icache_io_out_req_bits_wr; // @[MycpuCoreTop.scala 85:28]
  assign ysyx_22051110_AXIBridge_io_in_req_bits_addr = my_icache_io_out_req_bits_addr; // @[MycpuCoreTop.scala 85:28]
  assign ysyx_22051110_AXIBridge_io_in_req_bits_size = my_icache_io_out_req_bits_size; // @[MycpuCoreTop.scala 85:28]
  assign ysyx_22051110_AXIBridge_io_in_req_bits_wdata = my_icache_io_out_req_bits_wdata; // @[MycpuCoreTop.scala 85:28]
  assign ysyx_22051110_AXIBridge_io_in_req_bits_wstrb = my_icache_io_out_req_bits_wstrb; // @[MycpuCoreTop.scala 85:28]
  assign ysyx_22051110_AXIBridge_io_in_req_bits_mthrough = my_icache_io_out_req_bits_mthrough; // @[MycpuCoreTop.scala 85:28]
  assign ysyx_22051110_AXIBridge_io_out_ar_ready = my_arbiter_io_in_0_ar_ready; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_io_out_rd_valid = my_arbiter_io_in_0_rd_valid; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_io_out_rd_bits_rdata = my_arbiter_io_in_0_rd_bits_rdata; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_io_out_rd_bits_rlast = my_arbiter_io_in_0_rd_bits_rlast; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_io_out_aw_ready = my_arbiter_io_in_0_aw_ready; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_io_out_wt_ready = my_arbiter_io_in_0_wt_ready; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_io_out_b_valid = my_arbiter_io_in_0_b_valid; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_1_clock = clock;
  assign ysyx_22051110_AXIBridge_1_reset = reset;
  assign ysyx_22051110_AXIBridge_1_io_in_req_valid = my_mmc_io_axi_out_req_valid; // @[MycpuCoreTop.scala 90:28]
  assign ysyx_22051110_AXIBridge_1_io_in_req_bits_wr = my_mmc_io_axi_out_req_bits_wr; // @[MycpuCoreTop.scala 90:28]
  assign ysyx_22051110_AXIBridge_1_io_in_req_bits_addr = my_mmc_io_axi_out_req_bits_addr; // @[MycpuCoreTop.scala 90:28]
  assign ysyx_22051110_AXIBridge_1_io_in_req_bits_size = my_mmc_io_axi_out_req_bits_size; // @[MycpuCoreTop.scala 90:28]
  assign ysyx_22051110_AXIBridge_1_io_in_req_bits_wdata = my_mmc_io_axi_out_req_bits_wdata; // @[MycpuCoreTop.scala 90:28]
  assign ysyx_22051110_AXIBridge_1_io_in_req_bits_wstrb = my_mmc_io_axi_out_req_bits_wstrb; // @[MycpuCoreTop.scala 90:28]
  assign ysyx_22051110_AXIBridge_1_io_in_req_bits_mthrough = my_mmc_io_axi_out_req_bits_mthrough; // @[MycpuCoreTop.scala 90:28]
  assign ysyx_22051110_AXIBridge_1_io_out_ar_ready = my_arbiter_io_in_1_ar_ready; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_1_io_out_rd_valid = my_arbiter_io_in_1_rd_valid; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_1_io_out_rd_bits_rdata = my_arbiter_io_in_1_rd_bits_rdata; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_1_io_out_rd_bits_rlast = my_arbiter_io_in_1_rd_bits_rlast; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_1_io_out_aw_ready = my_arbiter_io_in_1_aw_ready; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_1_io_out_wt_ready = my_arbiter_io_in_1_wt_ready; // @[MycpuCoreTop.scala 95:29]
  assign ysyx_22051110_AXIBridge_1_io_out_b_valid = my_arbiter_io_in_1_b_valid; // @[MycpuCoreTop.scala 95:29]
  assign my_mmc_io_in_req_valid = my_dcache_io_out_req_valid; // @[MycpuCoreTop.scala 88:28]
  assign my_mmc_io_in_req_bits_wr = my_dcache_io_out_req_bits_wr; // @[MycpuCoreTop.scala 88:28]
  assign my_mmc_io_in_req_bits_addr = my_dcache_io_out_req_bits_addr; // @[MycpuCoreTop.scala 88:28]
  assign my_mmc_io_in_req_bits_size = my_dcache_io_out_req_bits_size; // @[MycpuCoreTop.scala 88:28]
  assign my_mmc_io_in_req_bits_wdata = my_dcache_io_out_req_bits_wdata; // @[MycpuCoreTop.scala 88:28]
  assign my_mmc_io_in_req_bits_wstrb = my_dcache_io_out_req_bits_wstrb; // @[MycpuCoreTop.scala 88:28]
  assign my_mmc_io_in_req_bits_mthrough = my_dcache_io_out_req_bits_mthrough; // @[MycpuCoreTop.scala 88:28]
  assign my_mmc_io_clint_out_clint_hit = my_clint_io_in_clint_hit; // @[MycpuCoreTop.scala 89:28]
  assign my_mmc_io_clint_out_ret_valid = my_clint_io_in_ret_valid; // @[MycpuCoreTop.scala 89:28]
  assign my_mmc_io_clint_out_rdata = my_clint_io_in_rdata; // @[MycpuCoreTop.scala 89:28]
  assign my_mmc_io_axi_out_req_ready = ysyx_22051110_AXIBridge_1_io_in_req_ready; // @[MycpuCoreTop.scala 90:28]
  assign my_mmc_io_axi_out_ret_rdata = ysyx_22051110_AXIBridge_1_io_in_ret_rdata; // @[MycpuCoreTop.scala 90:28]
  assign my_mmc_io_axi_out_ret_valid = ysyx_22051110_AXIBridge_1_io_in_ret_valid; // @[MycpuCoreTop.scala 90:28]
  assign my_mmc_io_axi_out_rlast = ysyx_22051110_AXIBridge_1_io_in_rlast; // @[MycpuCoreTop.scala 90:28]
  assign my_icache_clock = clock;
  assign my_icache_reset = reset;
  assign my_icache_io_in_req_valid = my_if_io_inst_mem_req_valid; // @[MycpuCoreTop.scala 84:28]
  assign my_icache_io_in_req_bits_addr = my_if_io_inst_mem_req_bits_addr; // @[MycpuCoreTop.scala 84:28]
  assign my_icache_io_in_req_bits_mthrough = my_if_io_inst_mem_req_bits_mthrough; // @[MycpuCoreTop.scala 84:28]
  assign my_icache_io_out_req_ready = ysyx_22051110_AXIBridge_io_in_req_ready; // @[MycpuCoreTop.scala 85:28]
  assign my_icache_io_out_ret_rdata = ysyx_22051110_AXIBridge_io_in_ret_rdata; // @[MycpuCoreTop.scala 85:28]
  assign my_icache_io_out_ret_valid = ysyx_22051110_AXIBridge_io_in_ret_valid; // @[MycpuCoreTop.scala 85:28]
  assign my_icache_io_out_rlast = ysyx_22051110_AXIBridge_io_in_rlast; // @[MycpuCoreTop.scala 85:28]
  assign my_icache_io_flush = my_dcache_io_flush; // @[MycpuCoreTop.scala 92:28]
  assign my_icache_io_cache_data_0_rdata = io_sram0_rdata; // @[MycpuCoreTop.scala 150:38]
  assign my_icache_io_cache_data_1_rdata = io_sram1_rdata; // @[MycpuCoreTop.scala 157:38]
  assign my_icache_io_cache_data_2_rdata = io_sram2_rdata; // @[MycpuCoreTop.scala 164:38]
  assign my_icache_io_cache_data_3_rdata = io_sram3_rdata; // @[MycpuCoreTop.scala 171:38]
  assign my_dcache_clock = clock;
  assign my_dcache_reset = reset;
  assign my_dcache_io_in_req_valid = my_mem_io_data_mem_req_valid; // @[MycpuCoreTop.scala 87:28]
  assign my_dcache_io_in_req_bits_wr = my_mem_io_data_mem_req_bits_wr; // @[MycpuCoreTop.scala 87:28]
  assign my_dcache_io_in_req_bits_addr = my_mem_io_data_mem_req_bits_addr; // @[MycpuCoreTop.scala 87:28]
  assign my_dcache_io_in_req_bits_size = my_mem_io_data_mem_req_bits_size; // @[MycpuCoreTop.scala 87:28]
  assign my_dcache_io_in_req_bits_wdata = my_mem_io_data_mem_req_bits_wdata; // @[MycpuCoreTop.scala 87:28]
  assign my_dcache_io_in_req_bits_wstrb = my_mem_io_data_mem_req_bits_wstrb; // @[MycpuCoreTop.scala 87:28]
  assign my_dcache_io_in_req_bits_mthrough = my_mem_io_data_mem_req_bits_mthrough; // @[MycpuCoreTop.scala 87:28]
  assign my_dcache_io_in_req_bits_fencei = my_mem_io_data_mem_req_bits_fencei; // @[MycpuCoreTop.scala 87:28]
  assign my_dcache_io_out_req_ready = my_mmc_io_in_req_ready; // @[MycpuCoreTop.scala 88:28]
  assign my_dcache_io_out_ret_rdata = my_mmc_io_in_ret_rdata; // @[MycpuCoreTop.scala 88:28]
  assign my_dcache_io_out_ret_valid = my_mmc_io_in_ret_valid; // @[MycpuCoreTop.scala 88:28]
  assign my_dcache_io_out_rlast = my_mmc_io_in_rlast; // @[MycpuCoreTop.scala 88:28]
  assign my_dcache_io_cache_data_0_rdata = io_sram4_rdata; // @[MycpuCoreTop.scala 178:38]
  assign my_dcache_io_cache_data_1_rdata = io_sram5_rdata; // @[MycpuCoreTop.scala 185:38]
  assign my_dcache_io_cache_data_2_rdata = io_sram6_rdata; // @[MycpuCoreTop.scala 192:38]
  assign my_dcache_io_cache_data_3_rdata = io_sram7_rdata; // @[MycpuCoreTop.scala 199:38]
  assign my_clint_clock = clock;
  assign my_clint_reset = reset;
  assign my_clint_io_in_en = my_mmc_io_clint_out_en; // @[MycpuCoreTop.scala 89:28]
  assign my_clint_io_in_wr = my_mmc_io_clint_out_wr; // @[MycpuCoreTop.scala 89:28]
  assign my_clint_io_in_addr = my_mmc_io_clint_out_addr; // @[MycpuCoreTop.scala 89:28]
  assign my_clint_io_in_wdata = my_mmc_io_clint_out_wdata; // @[MycpuCoreTop.scala 89:28]
  assign my_arbiter_clock = clock;
  assign my_arbiter_reset = reset;
  assign my_arbiter_io_in_0_ar_valid = ysyx_22051110_AXIBridge_io_out_ar_valid; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_ar_bits_araddr = ysyx_22051110_AXIBridge_io_out_ar_bits_araddr; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_ar_bits_arlen = ysyx_22051110_AXIBridge_io_out_ar_bits_arlen; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_ar_bits_arsize = ysyx_22051110_AXIBridge_io_out_ar_bits_arsize; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_rd_ready = ysyx_22051110_AXIBridge_io_out_rd_ready; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_aw_valid = ysyx_22051110_AXIBridge_io_out_aw_valid; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_aw_bits_awaddr = ysyx_22051110_AXIBridge_io_out_aw_bits_awaddr; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_aw_bits_awlen = ysyx_22051110_AXIBridge_io_out_aw_bits_awlen; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_aw_bits_awsize = ysyx_22051110_AXIBridge_io_out_aw_bits_awsize; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_wt_valid = ysyx_22051110_AXIBridge_io_out_wt_valid; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_wt_bits_wdata = ysyx_22051110_AXIBridge_io_out_wt_bits_wdata; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_wt_bits_wstrb = ysyx_22051110_AXIBridge_io_out_wt_bits_wstrb; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_wt_bits_wlast = ysyx_22051110_AXIBridge_io_out_wt_bits_wlast; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_0_b_ready = ysyx_22051110_AXIBridge_io_out_b_ready; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_ar_valid = ysyx_22051110_AXIBridge_1_io_out_ar_valid; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_ar_bits_araddr = ysyx_22051110_AXIBridge_1_io_out_ar_bits_araddr; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_ar_bits_arlen = ysyx_22051110_AXIBridge_1_io_out_ar_bits_arlen; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_ar_bits_arsize = ysyx_22051110_AXIBridge_1_io_out_ar_bits_arsize; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_rd_ready = ysyx_22051110_AXIBridge_1_io_out_rd_ready; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_aw_valid = ysyx_22051110_AXIBridge_1_io_out_aw_valid; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_aw_bits_awaddr = ysyx_22051110_AXIBridge_1_io_out_aw_bits_awaddr; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_aw_bits_awlen = ysyx_22051110_AXIBridge_1_io_out_aw_bits_awlen; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_aw_bits_awsize = ysyx_22051110_AXIBridge_1_io_out_aw_bits_awsize; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_wt_valid = ysyx_22051110_AXIBridge_1_io_out_wt_valid; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_wt_bits_wdata = ysyx_22051110_AXIBridge_1_io_out_wt_bits_wdata; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_wt_bits_wstrb = ysyx_22051110_AXIBridge_1_io_out_wt_bits_wstrb; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_wt_bits_wlast = ysyx_22051110_AXIBridge_1_io_out_wt_bits_wlast; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_in_1_b_ready = ysyx_22051110_AXIBridge_1_io_out_b_ready; // @[MycpuCoreTop.scala 95:29]
  assign my_arbiter_io_out_ar_ready = io_master_arready; // @[MycpuCoreTop.scala 129:32]
  assign my_arbiter_io_out_rd_valid = io_master_rvalid; // @[MycpuCoreTop.scala 138:32]
  assign my_arbiter_io_out_rd_bits_rdata = io_master_rdata; // @[MycpuCoreTop.scala 141:37]
  assign my_arbiter_io_out_rd_bits_rlast = io_master_rlast; // @[MycpuCoreTop.scala 142:37]
  assign my_arbiter_io_out_aw_ready = io_master_awready; // @[MycpuCoreTop.scala 110:32]
  assign my_arbiter_io_out_wt_ready = io_master_wready; // @[MycpuCoreTop.scala 118:32]
  assign my_arbiter_io_out_b_valid = io_master_bvalid; // @[MycpuCoreTop.scala 125:31]
endmodule
